The Seamless co-verification tool from Mentor Graphics has been customized to provide an efficient debug methodology for Virtex-II Pro Platform FPGAs.

The growth in the system-on-chip (SoC) market is fueled by the need to increase performance and reliability while reducing overall system costs.

With the introduction of the latest Xilinx Platform FPGAs, ASIC-style integration and performance is now available in programmable logic. This means that FPGA designers need access to newer electronic design automation (EDA) tools and methodologies to maintain design efficiency and productivity.

Hardware/software (HW/SW) co-verification is an example of one ASIC methodology that has recently gained relevance for platform FPGAs. In this article, I will introduce the concept of co-verification, and will describe the role, relevance, and realizable benefits in the context of programmable systems. I will also explain the actual development work we’ve done in cooperation with Mentor Graphics to extend existing HW/SW co-verification solutions to effectively target Xilinx devices.

The Debug Challenge
With as many as four IBM™ PowerPC™ 405 processors, ultra high-speed serial I/O technology, and up to 10 million system gates, Xilinx Platform FPGAs represent a paradigm shift in programmable platforms, as illustrated in Figure 1. These devices offer a unique and unprecedented combination of flexibility, performance, and integration to widely expand the size, scope, and range of applications that can now be deployed on FPGAs.

Just as leading-edge process technologies have helped silicon to achieve amazing capabilities, design software must keep pace by delivering productivity-enhancing tools that make it easier to design and debug. By various accounts, design verification is the most serious bottleneck engineers face today in delivering multimillion-gate SoCs. In the case of ASICs, it is not uncommon for verification teams to spend as much as 50% to 70% of their time and resources on the functional verification effort.

In the particular instance where a processor is part of a design, the interface between hardware and software becomes an area of increased focus and attention. Validation that the hardware and software will function correctly together becomes a critical part of the overall debug process. It is therefore important that specialized tools and methodologies be developed that promote debug efficiency and provide a streamlined approach to verification.

For a while now, HW/SW co-verification has been quite commonly used to debug ASIC SoC designs. Now, with an increasing number of FPGA design starts involving embedded processors, this technology is becoming meaningful and important for FPGA designers as well.

Co-Verification for Platform FPGAs
Mentor Graphics’ Seamless™ Co-Verification Environment (CVE) is the industry’s leading HW/SW co-verification tool – and now it supports the Xilinx Virtex-II Pro™ family of FPGAs. The basic concept behind co-verification is to merge the respective debug environments used by hardware and software teams into a single framework.

For example, a logic simulator is made to communicate with a software debugger, enabling you to get simultaneous control and visibility into the internals of the processor, as well as the hardware peripheral logic that surrounds it, as shown in Figure 2.

An efficient co-verification tool can help uncover a range of HW/SW interface problems, including:

• Initial startup and boot sequence errors (including RTOS boot)
• Processor and peripheral initialization and configuration problems
• Memory accessing and initialization problems
• Memory map and register map discrepancies
• Interrupt service routine errors.

1. The system has a processor executing software code that interacts with surrounding custom peripheral logic.
2. There is extensive interaction between software and hardware parts of the design during execution.
3. Both hardware and software engineering teams agree on using co-simulation early in the design stage.

Co-Verification vs. Simulation
Seamless CVE advances the concept of "functional simulation" in traditional logic-only FPGA designs to "co-verification" in processor-based Virtex-II Pro Platform FPGAs. This methodology establishes value for multiple design teams including hardware engineers (peripheral logic debug), embedded software engineers (application and firmware debug), and system designers (performance analysis and tuning). Let’s discuss some of the many advantages Seamless co-verification offers over simulation.

Faster Performance
Pure logic simulation can be used to simulate a design with a processor component. This is accomplished by including an RTL model of the processor to simulate the software code.

This approach, however, is painfully slow and not adequate to address all but the most basic debug requirements. The overall simulation speed is generally in the sub-100 Hz range.

Co-verification, on the other hand, is able to run simulation orders of magnitude faster. This speedup is achieved primarily through the use of clever tool optimizations and faster processor models known as instruction set simulators (ISSs).

To understand the concept of optimization, note that the real bottlenecks in simulation are due to the accurate but slow logic simulators. Every time the software needs to communicate with hardware, the transaction must go through a logic simulator. Because software runs on the ISS and it runs much faster, the software and ISS are always waiting for the hardware and logic simulator to catch up.

The Seamless tool bypasses this fundamental limitation by introducing the con-cept of a coherent memory server (CMS), shown in Figure 3. Using the CMS, the ISS is able to read and write to memory about 10,000 times faster than if it had to go through a logic simulator. Given that processor-to-logic interaction is mostly through read-write cycles to memory – fetching instructions, accessing peripheral registers, and such – the overall simulation speed can be dramatically increased by diverting most CPU-to-memory transactions to run through the faster CMS instead of through the logic simulator.

Only portions of code or regions of memory that are under active debug are run through the pin and cycle-accurate logic simulator. This means that the simulator bottleneck only factors in less than 1% of the software-hardware transactions, providing a significant overall throughput advantage over pure RTL simulation.

Increased Comprehension
To efficiently address debugging problems that span multiple teams, you need tools and methodologies that each team can relate to. For example, debugging processor code on an RTL model of the CPU is inherently inefficient and impractical.

In Seamless CVE, however, because a cycle-accurate ISS model replaces the RTL processor model, a symbolic debugger can be attached that enables interactive and graphical debugging capability. The standard features of a software debugger include the ability to step through source code (C and assembly), set breakpoints, and observe register and memory contents. This symbolic debugger gives you greater control and comprehension than what you would get by trying to achieve similar goals using the combination of a logic simulator and an HDL processor model.

Support for Abstract Models
Oftentimes, when very high data throughput is required to validate certain design functions, RTL models have to be replaced with faster, more abstract behavioral models. These high-speed models, usually written in C or C++, can interact with the ISS at very high speeds, allowing for complex protocols to be rapidly and comprehensively tested.

The Seamless co-verification tool has been extended to be able to plug in these behavioral models through its "C-Bridge" interface technology. By working less in the logic simulator and more with higher-level models, verification speeds can deliver significant performance gains. With increased simulation throughput, the virtual platform now gives you visibility into system performance and architectural trade-off issues at a very early stage in the design process. You can not only quickly validate functionality, but also analyze and tune important system attributes, such as bus bandwidth, latency, and contention – all leading to increased system performance.

Additional Co-Verification Benefits
With access to co-verification technology, processor-based designs are not only easier to debug, but the process starts much earlier in the design phase.

Find Problems Earlier
Design teams are highly motivated to identify and fix problems at an early stage in the design cycle. A well-known design axiom states: "The earlier a problem can be identified, the easier and cheaper it is to fix it."

Typically, designers cannot initiate software verification until a hardware prototype is available. As a consequence, when software verification occurs in a serial manner, HW/SW interaction problems may not be detected until much later in the design stage.

A virtual prototyping and debug environment removes this restriction by enabling product integration ahead of board and device availability, or even before the final design is committed. With the Seamless CVE, software teams do not have to wait for silicon before they can start developing and testing their portions of the design. As a result, problems can be found earlier and the time to working silicon is dramatically reduced.

Simplified Test Benches
To verify design functions, hardware engineers often write elaborate HDL test bench routines. These test benches can become very complex, and it is not uncommon for the test bench code size to approach that of the design itself. With co-verification, the ISS processor model allows test benches to be greatly simplified.

For hardware verification engineers testing protocols and device drivers, test benches are simplified, because actual embedded software code – and not contrived test bench code – is driving the hardware circuits.

Similarly, software engineers do not have to resort to writing stub code. Actual hardware devices provide real-life responses to calls made to hardware. Overall, this leads to fuller and more comprehensive test coverage, leading in turn to increased confidence in the working of the design in silicon in the first instance.

Greater Runtime Control
An important attribute of debugging in the virtual domain is the ability to "stop time." As a result, it is easily possible to simultaneously observe and modify the internal values of the CPU registers, as well as those of the hardware device registers with which the processor is communicating. This ability to freeze and synchronize the hardware and software domains offers the ultimate in control and observability – and it is invaluable in efficiently helping debug complex and intricate transactions.

Virtex-II Pro Enhancements
In supporting Xilinx Virtex-II Pro FPGAs, the Seamless tool is able to largely leverage off its existing support for the IBM PowerPC 405 core. However, subtle differences in Virtex-II Pro devices have required customized enhancements to the IBM 405 Processor Support Package (PSP) and the Seamless CVE product to provide you with an efficient and easy out-of-the-box experience, as shown in Figure 4.

First, the PowerPC 405 ISS model from Mentor Graphics had to be matched with the Xilinx version of the PowerPC 405 core, which resolved some of the pin differences.

Additionally, Virtex-II Pro devices have dedicated on-chip memory (OCM) controller circuitry that, in the actual silicon, is tied to the OCM port of the PowerPC 405 core. The same connection had to be stitched in the Seamless environment to the PowerPC 405 ISS.

Xilinx embedded memory blocks (block RAMs) also had to be specially coded to be compatible with the Seamless coherent memory server. This was accomplished by inserting special hooks into the HDL memory models for the block RAMs.

Finally, a conscious attempt was made to ease the learning curve for engineers already familiar with Virtex-II Pro Development Kit (V2PDK) flows. Three of the reference designs included in V2PDK were ported to the Seamless environment. This allows you to not only get a jump-start in understanding co-verification flows, but also the ability to compare and contrast co-verification with pure logic simulation.

All these enhancements are rolled into a customized PSP that represents the final integrated module, which can be used with the standard Seamless kernel.

In addition, a special Xilinx-only version of the Seamless CVE product has been introduced. This bundle includes the Seamless kernel and the PSP, and it is designed specifically for the Virtex-II Pro environment.

To prepare a design to run in the Seamless co-verification environment, the following steps must be taken:

1. Instantiate the Seamless PowerPC bus interface models into your Verilog™/VHDL design (replacing the PPC Swift model).
2. Provide the Seamless tool with access to the "Seamless-ready" block RAM memory models. These models mirror the HDL models but are enhanced with API hooks, which allows them to communicate with the coherent memory server.
3. Input the systems memory map into the Seamless graphical user interface and define startup options for the hardware simulator.
4. Load the compiled software executable (.elf with -gdwarf) into the software debugger and start the session.

However, there are classes of problems involving behavior that can only be captured when the processor runs at full speed. In this regard, platform FPGAs serve as a perfect complement to virtual platform debug techniques. Designs can be downloaded into FPGA silicon for validation at full system speeds.

If problems escaped earlier attention, you can debug in-system with the Xilinx ChipScope™ Pro interactive logic analyzer, or you can go back to the co-verification environment for a more controlled analysis. Design errors can be fixed and re-implemented in silicon without incurring the huge delays and costly mask re-spins common with ASIC design flows.

Conclusion
The current generation of Xilinx Platform FPGAs with powerful RISC processors and multimillion-gate capacities requires powerful and matching co-verification methodologies. With the availability of Mentor Graphics’ Seamless CVE, you now have access to an ASIC-strength, best-in-class debug solution.

Seamless CVE provides an efficient and easy-to-use methodology that can integrate, verify, and debug hardware and software interactions very early in the design cycle – thus preserving and enhancing the critical time-to-market advantage of FPGAs. To learn more about Seamless co-verification, go to www.mentor.com/seamless/fpga/.

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