By optimizing its timing-driven synthesis tool for Spartan-3 devices, the Synplicity Synplify Pro FPGA synthesis tool makes it possible to meet timing constraints and deliver significant area savings.

Xilinx Spartan™-3 devices let you take on a new set of applications once reserved for the ASIC domain – and complete those applications quickly and cost effectively. Closing timing is a challenge on large devices; however, Synplicity has made the leap to the next performance level.

The Synplicity timing-driven synthesis solution has been optimized for the Spartan-3 family. It provides optimal implementations of your HDL to increase performance, reduce area, and drive down the solution cost.

Best of Both Worlds
The Synplify Pro® FPGA synthesis tool is truly timing driven. Critical paths are speed-optimized to meet timing constraints. Non-critical paths are optimized for area. Once your timing constraints are met, the Synplify Pro tool turns its attention to area optimization. This allows you to meet your timing goal in the smallest device possible. Timing-driven synthesis delivers huge area savings and still meets timing constraints.

Figure 1 shows a graph of requested and actual maximum operating frequency (Fmax) for the place-and-route (PAR) results of a design run through the Synplify Pro synthesis tool. The tool’s estimates follow the requested frequency line until other critical paths start appearing that the tool cannot optimize. At that point, Fmax starts to degrade.

Figure 2 shows the LUT (look-up table) count for the same design. The results underline the importance of true timing-driven synthesis. When the requested frequency is low, the LUT count is low. The LUT count only starts to increase when the requested frequency is raised. This performance-on-demand feature can drastically reduce area while maintaining performance.

The Synplify Pro tool can also reduce area by automatically mapping logic to dedicated resources within the Spartan-3 architecture. The tool extracts ROMs, RAMs, SRL™ (scan ring linker) modules, and global control resources, among others. Extracting these logic modules increases performance and in most cases, decreases the number of logic gates in slices, which in turn reduces the LUT count.

Three Ways to Win
The Synplify Pro synthesis solution reduces Spartan-3-based design costs for three different design scenarios:

1. For designs with challenging performance goals, the tool offers advanced logic optimizations to meet your requested frequency – and still allows you to choose a slower speed-grade device. Switching to a lower speed-grade device can drastically reduce costs on high production runs.
2. For designs with both performance and device-size goals, the Synplify Pro engine provides performance on demand. As Figures 1 and 2 illustrate, when requested performance is non-taxing, the LUT count remains very low, which lets you choose a
3. When modifications are required to an existing FPGA in a system, the cost can be high. In particular, when modifications fail to place or route properly, the most likely option is a complete redesign at enormous cost. The Synplify Pro tool reduces the probability of modification failure with its performance benefits and performance-on-demand area savings. It is much easier to route a less full device. Because the Synplify Pro engine can meet the performance by utilizing a small device, there is a higher probability of the modified design being successfully implemented with the low utilization.

ASIC to FPGA Migration
Because Spartan-3 devices have a very high gates-per-dollar ratio, ASIC designers are increasingly adapting to FPGA solutions. In doing so, they also reap the benefits of reprogrammability and zero NRE (non-recurring engineering) costs.

Among the drawbacks of the ASIC-to-FPGA flow are coding structure and instantiated components. Synplicity has been providing a solution (the Certify® product) for ASIC prototyping in an FPGA that addresses both of these issues. But for generic ASIC code, the biggest pitfall is gated clocks.

With the release of Version 7.3, the Synplify Pro FPGA synthesis tool can automatically convert the gated clock structures commonly used in ASICs so that they map to clock enables in Xilinx devices while making use of global routing resources. This feature has two primary benefits for ASIC/FPGA designers:

1. Gated clock conversion eases the pain of migrating ASIC code.
2. The tool automatically provides higher performance and better utilization, because global routing resources are used instead of internal high fanout nets.

Save Money on Your Next Spartan-3 Design
The performance of the Synplify Pro solution, coupled with industry-leading FPGAs from Xilinx, gives you the ability to meet aggressive performance goals on time and on budget.

To test the Synplify Pro tool and see the cost savings for yourself, download the Synplify Pro tool at www.synplicity.com/downloads/download1.html.

When informed that you do not have a license, follow the subsequent instructions and send the information to license@synplicity.com. Synplicity will send you a temporary license immediately.

Also, to be sure you get the most from the Synplify Pro FPGA synthesis solution, download and read "Benchmarking Synplify and Synplify Pro Software" at www.synplicity.com/literature/pdf/benchmarking_synplify.pdf.

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