Hier Design’s PlanAhead software eliminates many problems encountered in high-end FPGA designs.

As an FPGA designer, you probably face many of the same problems that have plagued ASIC designers, including lengthy, repetitive place-and-route (PAR) runs; unpredictable route times; and difficulty maintaining performance throughout frequent design iterations. These problems can delay or even prevent you from completing your design, resulting in increased engineering costs and longer time to market.

ASIC-style methodologies, however, enable you to divide and conquer your complex FPGA designs by breaking them into component blocks, shortening the length and increasing the predictability of routing. As shown in Figure 1, these methodologies also allow you to analyze, detect, and correct potential implementation problems before PAR.

An ASIC-style methodology offers the following benefits:

• Quicker incremental design changes or engineering change orders (ECOs)
• Faster, more predictable PAR
• Fewer iterations
• Improved performance
• Tighter utilization control
• Better teamwork
• IP reuse.

Quicker Incremental Design Changes
When you make even minor changes to a given logic block with a flat methodology, you must redo place-and-route for the entire design. With today’s larger FPGA netlists, 50 or more PAR iterations – at eight or more hours apiece – are common. This adds up to a significant amount of wasted time. With an ASIC-style design methodology, you can use hierarchy to reduce PAR time. By breaking your designs into smaller pieces, or blocks, you don’t need to run PAR on the entire design each time you make an incremental design change. Instead, you can just run PAR on the block or blocks that have changed, leaving the rest intact.

As an example, see Figure 2. In the flattened methodology on the left, a logic block is highlighted in yellow. Notice how it is scattered over nearly the whole chip. Any design change in this logic block means that you must PAR the entire flattened design all over again. Consequently, design performance may change significantly.

In the hierarchical methodology on the right, the same logic block is highlighted in yellow. Note that it is localized within a distinct area of the chip. If you make a change to this logic block, you only need to PAR this block. The rest of the design and its performance remain largely unaffected.

Faster, More Predictable PAR
Without hierarchy, PAR algorithms on a flat design are less efficient and need far more time to operate. Yet traditional FPGA design tools still primarily operate in that mode. An ASIC-style methodology allows you to define area groups. These groups break the design into smaller pieces that PAR algorithms can more easily handle. Because individual blocks are more manageable, PAR takes less time to complete the overall design.

In the traditional FPGA design process, the duration and number of PAR runs have not only become a bottleneck – the results themselves are unpredictable and unreliable. Even if you make no design changes, one run may produce a faster or slower design than previous runs because of the randomness of the routing algorithms.

Some designers using flat methodologies try to reach timing goals using multiple routing runs, each with different random seed values, hoping that one of them will produce a design with adequate performance.

A hierarchical methodology, however, offers a more deterministic process by enabling you to define area groups to steer PAR toward acceptable timing.

You can also lock in placement results for individual blocks that have already met timing goals, so that subsequent PAR iterations do not change the performance of the locked blocks. This serves to further stabilize the PAR process, ensuring more reliable and predictable results.

Fewer Design Iterations
If you are designing large FPGAs, you probably iterate the physical implementation many times to meet multiple simultaneous requirements. Such requirements may include:

• Connectivity
• Utilization
• I/O placement
• Clock regions
• Power
• Timing.

ASIC-style methodologies help you quickly reach your requirements – prior to PAR – through early design analysis, tightly coupled with floorplanning. With floorplanning and early analysis, you can substantially reduce the number and length of PAR iterations.

In Figure 3, early connectivity analysis in the PlanAhead software (left screen) provides visual clues: The thickness and color of bundled lines represent the nets between blocks. You can see – and fix – routing congestion before PAR. You can quickly adjust the floorplan by moving, rearranging, and combining blocks in the physical hierarchy (right screen). Moreover, you can manipulate the physical hierarchy independently from the logical hierarchy.

Using this process, the PAR algorithms now have the necessary partitioning, block arrangement, and constraints to guide them to success.

Improved Design Performance
When designing with today’s large FPGAs, you may encounter timing knots, long critical paths spanning hierarchy, complex clocking, and high fan-out – making timing goals more difficult to meet. ASIC designers have successfully overcome these kinds of problems through techniques now available to FPGA designers.

Static timing analysis enables you to quickly visualize potential timing problems early in the design cycle, before PAR. Floorplanning lets you make adjustments to avoid these timing problems by controlling logic migration and shortening connectivity paths.

Static timing analysis also highlights critical paths in the floor plan so that you can fix them by using constraints or manually rearranging the path instances.

In a misguided effort, some ASIC-style methodologies attempt to improve performance by floorplanning before synthesis. This is not a good idea, because there may be large errors in the estimates of design performance. In contrast, PlanAhead software acquires more accurate timing information at the highest impact point in the design flow, thereby maximizing performance improvement.

The PlanAhead software also includes physical optimization capability to address implementation problems that may arise later in the design cycle, post-PAR. With the PlanAhead tools, you can still adjust placement at the block or leaf level to reach performance goals. You can then run timing analysis to see if performance has improved. With this process you get nearly instantaneous feedback, rather than waiting for hours for PAR to finish.

Methodology Results Example
Table 1 demonstrates the advantages of adopting an ASIC-style methodology and using the PlanAhead design and optimization software. Our example includes hierarchical design combined with floorplanning and integrated analysis.

Table 1 – Methodology results comparison using PlanAhead design and optimization software

Methodology Used	Timing	Place & Route	Runtime Runtime Reduction
Traditional flattened netlist	-0.88 ns negative slack	5.0 hrs.
With floorplanning and analysis	Meets timing	3.5 hrs.	30%
With incremental ECO capability	Meets timing	40 min.	87%

In this example, our customer’s designers implemented a wireless communications chip with the Virtex™-II 2V6000 platform as their target device. Using a traditional flat methodology, they had 18 timing errors.

By using a block-based, incremental, ECO methodology, their PAR time was 87% faster than their flat methodology. By creating a more efficient floor plan, they were able to meet all of their timing goals. Slice utilization remained a constant 98% throughout.

The first row of Table 1 displays PAR time and design performance using a traditional flattened methodology. The second row demonstrates the benefits of floorplanning. And the third row shows even more benefits by combining floorplanning with an incremental ECO design methodology.

The runtime column lists the total CPU time used by Xilinx PAR. The timing column indicates whether the design was able to meet performance goals.

Tighter Utilization Control
Utilization is an important aspect of FPGA design. In some cases, designers crowd as much logic into a given device as possible to meet production volume requirements.

In other cases, they must leave some space in the FPGA to accommodate bug fixes, naturally occurring design changes, ECOs, or future field upgrades. Leaving room for change is essential for electronic devices with long serviceable life cycles.

Using block-based hierarchical design techniques makes it easier to control utilization. To maximize utilization, you can set the controls at a given utilization level and run a block-level PAR. If it produces successful results, you can increase the utilization setting, which shrinks the block, and then run another block-level PAR.

You can continue this process until the PAR fails, which means you have achieved the maximum possible utilization for the given block. By applying Xilinx area group compression constraints on blocks that are not timing critical, you can also significantly increase utilization.

A wise approach is to leave more space in blocks that have yet to be verified, so you can accommodate anticipated bug fixes.

You might, however, desire a higher utilization setting in blocks that are already field-proven, because it is less likely that extra space will be needed to fix bugs within them.

Teamwork and IP Reuse
Like ASIC designers, you can expedite design time by working as a team and reusing intellectual property (IP) from previous designs. The PlanAhead software provides an ASIC-style hierarchical methodology that facilitates this kind of teamwork.

You can use a block-based approach to divide the work into more manageable blocks and assign responsibilities of designing them to individual team members. You can also reuse blocks (also known as IP cores) from previous designs, or even purchase blocks from a third party to save design and verification time.

When working as such a team, you can begin the physical design process much earlier. You can sequentially implement and assemble the design, beginning with the most critical blocks, as shown in Figure 4. Successively, you can PAR the blocks as designers complete their assignments.

Using ASIC-style methodologies, you can fully characterize design blocks by freezing the placement within them so that power, timing, and other characteristics remain constant. Thus, it’s possible to reuse them with consistent results in similar FPGA devices. Because you know that these blocks meet your physical requirements, you can quickly connect them to form larger designs that also meet your requirements.

ASIC designers refer to this type of design as a system-on-chip methodology, and it is particularly valuable if you are an ASIC designer using FPGAs for prototyping. To significantly reduce your overall verification time, use the PlanAhead analysis and floorplanning software to lock placement within pre-characterized IP blocks and connect them together. Because you already know these blocks meet timing and other design requirements, you can create a working ASIC prototype much more quickly.

Conclusion
FPGAs have become so complex that you may be encountering ASIC-size design bottlenecks. You can overcome these problems by adopting proven ASIC-style design methodologies. Hierarchical design enables you to make fast incremental changes, and early analysis allows you to fix problems prior to place-and-route.

You can closely control utilization, packing designs ever tighter, or leave extra room for bug fixes, ECOs, or planned upgrades for products that have a long field or shelf life.

Finally, you can work as a team and shorten design and verification time by reusing blocks of pre-characterized IP. To learn more about the PlanAhead hierarchical design and physical optimization software, visit the Hier Design website at www.hierdesign.com.

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