Conserve FPGA resources in cost-sensitive designs with Synplicity timing-driven synthesis solutions.

Often, simply being first to market with an excellent product can assure its success. However, effectively harnessing available resources to allow for less expensive parts – and thus a less expensive overall solution – can also give you a significant advantage over a competitor.

The Synplify™ FPGA synthesis solutions and Synplify Pro™ advanced FPGA synthesis solutions from Synplicity™ have many features that enable you to effectively use the resources in FPGAs. For example, you can set constraints for timing-driven synthesis that may allow you to purchase slower speed grade parts without compromising on performance or quality. The Synplify FPGA synthesis solution and Synplify Pro advanced FPGA synthesis solutions offer a perfect fit for the high-volume, low-cost Spartan™ FPGAs, and the advanced Virtex™ series of FPGAs.

Spartan/Virtex Architecture
Spartan-II series FPGAs are based on the Xilinx Virtex architecture. Each FPGA has a number of clock delay locked loops (CLKDLL) for clock management (each CLKDLL driving one of four global clock lines) and block RAM of 4 Kb each.

Furthermore, the basic Virtex architecture can be broken down into “slices,” comprising two RAM-based 4-input look-up tables (LUT), two registers, and dedicated “carry logic” used for arithmetic operations (Figure 1). You can configure the LUT as distributed RAM, a shift register LUT (SRL) with a programmable latency of as many as 16 clock cycles, or an LUT for a 4-input Boolean function. Inside of every input/output block (IOB) are three flip-flops so that the data coming into and leaving the IOB can be registered, thereby increasing the overall maximum frequency.

Spartan-3 series FPGAs are based on the more advanced Xilinx Virtex-II platform FPGA hardware. The difference is that the CLKDLL has added functionality, along with a total of 16 global clock lines (eight global lines in the Spartan-3). The block RAM is larger, with 18 Kb of memory. Platform FPGAs have more registers in the IOBs to accommodate dual data rate (DDR) applications. The Virtex-II architecture also includes embedded multipliers that can be synchronous or asynchronous.

The Synplify and Synplify Pro tools take advantage of the hardware present in the Spartan and Virtex families to ensure optimal area and speed results.

Timing-Driven Synthesis
The Synplify Pro solution is an advanced synthesis tool that performs timing optimizations based on the timing constraints entered. Optimizations are based on – but not limited to – offset and period constraints. Timing constraints are entered in a constraints file (text or GUI entry) or through a tool command language (TCL) script.

Because Synplify Pro software is timing driven, you must provide realistic timing constraints. Avoid over-constraining by asking for more than 10% or 15% of what you really need; in other words, if you need 100 MHz, enter 100 MHz or perhaps 110 MHz. The timing-driven aspect of the Synplify Pro software first meets your timing constraints and once met, minimizes area. This allows you to achieve your performance goal while using the smallest, lowest cost device.

Synplicity’s SCOPE® (synthesis constraints optimization environment) GUI allows you to easily manipulate constraints from the register transfer level (RTL) viewer into the spreadsheet. Just click and drag any object into the spreadsheet and apply the appropriate constraint, or select the objects from pull-down menus in the spreadsheet’s individual cells (Figure 2).

The SCOPE interface provides a single location for both synthesis and place-and-route (PAR) constraints, which are passed along to the Xilinx PAR tool. Clocks, inputs, and outputs are all automatically loaded into the SCOPE utility for fast and easy constraint entry.

The Synplify Pro synthesis tool has options that allow you to manipulate registers and increase the maximum frequency in your design. One such option is retiming. With the retiming switch on, the Synplify Pro program moves existing registers through combinatorial logic to balance timing delay between registers. This option is very helpful when your design is pipelined.

Other features include the inference of SRLs (which saves resources) and IOB flip-flops: You can control both through the use of the synthesis directives syn_srlstyle and syn_useioff.

Synplify Pro software also includes FSM Explorer and FSM Compiler. With FSM Explorer, the Synplify Pro synthesis tool locates the design’s finite state machines (FSM) and determines the optimal encoding style for the FSM to meet timing constraints.

To explore different state machine encoding styles, just turn off FSM Explorer and select the encoding style by using the syn_encoding directive, along with the choices default, one-hot, gray, sequential, and safe. When selecting default, a predetermined encoding style will be used based on the number of states in the FSM.

Incremental Design
Synplicity’s MultiPoint™ technology allows you to work incrementally on individual modules in your design – without having to re-synthesize the entire design each time you make a change. The MultiPoint flow provides a superior approach to incremental design that provides stability during design changes without com-promising the quality of results. You can set the compile points in the constraints file by manual entry or through the SCOPE interface (Figure 3).

The MultiPoint technology is intelligent, and knows when logic changes require recompilation. For example, an HDL syntax change or an added comment will not trigger recompilation, but a change that alters the logic will.

You can use MultiPoint synthesis in conjunction with the incremental design flow process in the Xilinx implementation tool, along with “cross probing” to better achieve timing closing.

Entering realistic timing constraints is important, because once timing constraints are met, the Synplify Pro tool works on area optimizations. If your critical path does not go through your state machine, it’s easy to try a different encoding style that may not be as efficient in timing but is more efficient in area, freeing up resources in the critical path.

Synplify Pro software further optimizes your HDL code with its numerous inference templates. With inference templates, the Synplify Pro program takes advantage of the resources available in FPGAs. Depending on how you set certain synthesis directives, the Synplify software infers SRLs, block multipliers, block RAM, and ROM in block RAM, saving LUTs for the combinatorial logic.

Conclusion
In today’s economic climate, cost savings are paramount. Together, Synplicity and Xilinx offer a combination of synthesis software optimized for timing, area, and cost savings on the best price-for-performance FPGAs available. To see what the Synplify and Synplify Pro synthesis tools can do for your Xilinx FPGA design, download free, fully functional evaluation copies of the Synplify and Synplify Pro solutions from www.synplicity.com/downloads/. For additional information on the Spartan-3 family of FPGAs, visit www.xilinx.com/Spartan3/. To learn more about Virtex FPGAs, go to www.xilinx.com/virtex2/.

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