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Xilinx Design Services assists in the development of a new eye care technology.
Optos PLC, a revolutionary eye care technology
company, selected Xilinx Virtex-II
Pro™ FPGAs to be at the heart of their
wide-field visual imaging system. To lower
the risk, reduce the learning curve, and
meet their time-to-market requirements for
this new technology, Optos engaged Xilinx
Design Services (XDS) to help them plan,
design, implement, and deliver their complex
solution.
The Optos Panoramic System comprises
two IBM™ PowerPC™ 405 microprocessors
and multiple proprietary
interfaces, as well as industry standard
interfaces. The design utilizes the latest
technology, tools, and software provided by
Xilinx and gave XDS the opportunity to
apply its system, hardware, and embedded
software knowledge, along with its project
management expertise, to meet the timeto-
market requirements.
The Design Challenge
For Optos, the challenge was to find a technology
that provided them with the technical
features to take their system from concept
to reality. The system is used by a
qualified operator to take a scan of the
patient’s eye while they look at a target presented
on an LCD panel. This image capture
uses Optos’ patented technology in
wide-field visual imaging and transfers the
data to a microprocessor. The processor is
used for storage of patient data and processing
by the operator.
The challenge for XDS was to design,
develop, test, simulate, integrate, and
bring up the hardware and software on a
single platform to enable a complete connectivity
solution addressing all layers of
the Optos application. The solution also
had to be scaleable for future features and
upgrades. XDS was also required to meet
budget constraints.
The Teams
The Xilinx Design Services team worked
with the Optos engineering team to set the
system requirements and to agree on a schedule
and deliverables for the project. Over the
period of the project, the XDS project manager
worked with the Optos project management
team to ensure that milestones were
delivered and that information flowed
smoothly between the two teams.
Optos
Optos was founded to develop a technology
that will provide ophthalmologists
and optometrists with improved
image capture and analysis capability for
the early detection and prevention of eye
disease. Optos’ patented technology in
wide-field visual imaging is unique.
Their business strategy is to make their
visual imaging system available to the
greatest number of practitioners, thus
allowing an overall improvement in eye
care and early disease detection for a far
greater number of people.
The Optos headquarters in
Dunfermline, United Kingdom, is the base
for research and development of the
Panoramic diagnostic ophthalmic apparatus,
the technology behind Optomap
Retinal Images.
Xilinx Design Services
Optos contracted XDS to design and deliver
the Virtex-II Pro 2VP20 design. By doing
so, they reduced the risk and learning curve
for this new technology, and they ensured
they would meet their time-to-market goal.
XDS gathered a team of experienced codesign
engineers with in-depth knowledge
of project management, embedded software design, FPGA design, co-design tools, IP
cores, and platform FPGAs.
The final delivery to Optos included
the source code for the embedded
test software, HDL designs, design
scripts, HDL test vectors, simulation
test software, build scripts, and associated
testbenches. The delivery specifications
also included all associated
project documentation: project plan,
design specifications, testbench strategy,
software specifications, memory
map, and verification plan.
The Panoramic System
Figure 1 shows the basic Panoramic system
design, which includes:
- System control processor (SCP),
described as System Configuration
and Control in the diagram legend
- Camera and digital signal processing
(DSP) components, described as
DSP and Camera Logic
- transceiver (MGT) data and PCI,
described as High-Speed Data Logic.
Each section interacts with the others,
but is not 100 percent interdependent.
In Figure 2 you can see a more
detailed diagram of the system that XDS
designed. The outer color blocks in
Figure 2 show the division of the logic
in the system. The interface between the
two main blocks shown in Figure 2 was
through the use of device control registers
(DCRs) accessed and controlled by
both the SCP and associated hardware.
System Control Processor
The main function of the SCP is system
configuration management, coordination,
status reporting, and control of the timing
of events based on inputs. It starts image
capture, and controls LCD display and
other logic through registers in the system.
The main technical blocks of the SCP
perform the following functions:
- Communicate with the Intel™ x86
operating system environment over
PCI and RS-232 connections
- Configure the LCD panel and camera
interfaces via IIC
- Display images on the LCD panel
- Communicate with peripheral subsystems
via SPI
- Boot from internal Virtex-II Pro block
RAM and load application from external
flash memory to ZBT RAM before
running it
- Schedule and control events in the
application software via interrupts and
GPIO
- Use DCR registers to gather status and
control operations in other sections.
DSP and Camera Logic
The camera interfaces are required to support
30 frames per second (fps) of 640 x
480 pixels, requiring bandwidths greater
than 9 Mbps for each camera. The data is
stored locally in ZBT RAM so that a DSP
algorithm running on the second
PowerPC 405 microprocessor can be
applied to the data. While the data is being
received from the cameras, it is also copied
to DDR SDRAM for transmission over
the PCI to the host x86 memory space.
High-Speed Data Logic
RocketIO™ MGTs are used to receive
high-speed data from three peripheral
boards, each transmitting data from a single
MGT on a Virtex-II Pro 2VP7. The MGT
data transfers are initiated by an external
system triggered by the operator. This event
is synchronized using interrupts to the SCP.
The data from the three MGTs is formatted
in the Virtex-II Pro device and used to form
a larger data packet, which is then stored in
DDR SDRAM for transmission over PCI.
The PCI section is used to transfer all
the data stored in the DDR SDRAM to
the x86 host processor environment.
XDS designed a number of proprietary
hardware blocks to control the flow of
data from DDR SDRAM to the OPBPCI
core and over to the host x86 memory
space. Configuration and status of the
PCI core is carried out by the SCP
through DCR registers.
Tools
During this project, XDS used several software
tools to create the Panoramic system,
to simulate the design, and to manage the
development environment to ensure traceability
and quality releases. The tools used
are listed in Table 1.
Table 1 – Software used to develop, simulate, and manage
the development environment of the Panoramic system
Function
| Tool Used
| Vendor
|
| VHDL Design, Compile, Test | ISE 5.2i | Xilinx |
| Software Design, Compile, Test | EDK 3.2 | Xilinx |
| Logic and Software Simulation | MTI 5.6d | Mentor Graphics |
| Version Management | CVS | Open Source |
Test and Verification
When designing a project of this size, test
and verification are of paramount importance
to the successful completion of the
project. The XDS team focused a large
number of resources to ensure the design
met Optos’ requirements.
The team developed a full testbench that
would fit around the design (shown in Figure
2). This testbench was designed to simulate
every interface in the design. It consisted of a
PowerPC microprocessor with peripheral
cores to test protocols and communication
interfaces. Both the design and the testbench
used the swift model for the PowerPC microprocessor
to run the software during simulation.
A swift model is a cycle-accurate
simulation model that can interpret
PowerPC instructions and act accordingly.
Two software applications were used to
test the system in simulation. The first ran
on the testbench and the second ran on the
system under test (SUT).
The function of the SUT application is
to interact with the peripheral cores and
to drive the inputs and outputs of the
SUT. The application in the testbench
interacts with the SUT in the following
manner:
- Data received from the SUT is stored
in memory.
- Protocol data is decoded, stored, and
replied to, if appropriate.
The application for the SUT allows
hardware design engineers
to control many
different features and
to run a suite of tests in
any order required. The
XDS team also
designed tests to verify
the pure hardware
interfaces without
interaction with the
applications.
All functionality was
tested at unit, functional,
and system level. The
tests were all documented in the test and verification
plan, which was approved by Optos
before the system design phase began.
Conclusion
With Xilinx Design Services, you get a
highly skilled and experienced team that
will help get you to market faster by bridging
the learning curve, delivering quality
on-time designs, and working in close
contact with your development team.
In a letter to the engineers at Xilinx
Design Services, David Cairns, technical
director at Optos, wrote, “I have been
impressed with Xilinx Design Services.
Their commitment to quality and high
standards has eased transition into production.
XDS went the extra mile, and we
could not have achieved our design goals
without their help.”
For more information about Xilinx
Design Services, visit www.xilinx.com/xds.
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