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While designing the Avnet Design Services
Virtex-II Pro™ 3.125 Gbps Aurora Design
Kit, we found that there were a variety of
options for the interface between the
Virtex-II Pro multi-gigabit transceivers
(MGTs) and the SubMiniature version A
(SMA) connectors on the board. After trying
a few of these options and measuring
the results on the prototype board, we discovered
that the signal integrity performance
of the interface varied widely
depending on the type of SMA connector
used, the location, and characteristics of the
board traces.
In this article, we’ll review several specific
design options and their impact on signal
integrity. Our test results will show why the
final “optimal” design was selected. We’ll
also provide detailed measurements on the
signal integrity of the final design.
Avnet Virtex-II Pro Aurora Design Kit
The Aurora Design Kit includes the Avnet
Design Services Virtex-II Pro evaluation
board and its associated documentation,
board support package, applications code,
and example designs. The Aurora reference
design has been ported to the board; an
example design communicating between
serial ports at 3.125 Gbps demonstrates the
features and capabilities of the design kit.
The circuit board used in the design kit is
shown in Figure 1.
The hardware features of the evaluation
board include the user FPGA, on-board
memory, on-board communications,
expansion, and configuration. A complete
block diagram of the board’s hardware
components is shown in Figure 2.
The user FPGA is a Virtex-II Pro
XC2VP7-FF896 device that includes an
embedded PowerPC™ processor, eight
high-speed serial I/O channels, and
RocketIO™ MGTs.
The high-speed communications functions
of the board include eight SMA connectors
(TX/RX pairs for two RocketIO
ports) with board-configurable loop-back
for two RocketIO transceivers and pads for
four additional RocketIO ports.
The connectors featured on board
include two 140-pin general-purpose I/O
expansion connectors (AvBus), up to 30
LVDS pairs, and a standard 50-pin 0.1-inch header for custom expansion.
Memory includes Micron™ DDR
SDRAM (64 MB) for use as code storage
space for the PowerPC and packet storage
for serial I/O ports. Communication can
also occur over a standard RS-232 serial
port for simple monitor or debug functions.
An included 5.0V AC/DC power supply
provides up to 22.5W for the on-board Texas
Instruments™ 3.3V 6A module and
National Semiconductor™ linear regulators.
You can configure the FPGA via two
Xilinx XC18V04-VQ44 PROMs, a
Parallel IV cable for JTAG, and fly-wire
support for Parallel-III and Multilinx™
configuration cables.
Mictor™ connectors are available to
access the remaining high-speed I/O signals
(MGTs) on the device for test or characterization.
Prototype Design
When we first received the prototype
design from the manufacturing house, we
tested the MGT-to-SMA connections. In
preliminary testing, we used a loop-back
connection over an SMA cable from one
MGT to another. No FR4 of significant
length was inserted.
Test packets were simple 00 to FF data
words (256 bytes) with idle sequences
(k28.5, d21.4, d21.5, d21.5) between
packets. We captured eye diagrams using
the repeating idle sequence (Figure 3).
Although the eye opening is fairly clean,
the pattern is a repeating idle sequence and
thus doesn’t provide a very extensive test.
During our initial prototype testing, we
sent several thousand packets successfully.
However, testing additional boards revealed that performance was not repeatable,
and in fact was much worse for the
majority of boards. Because these initial
boards used -5 speed grade parts, we surmised
that the errors could be attributed to
the 2.0 Gbps limitation of the -5 speed
grade devices.
Yet procurement of -6 speed grade parts
revealed that this was not the case; a substantial
number of errors continued to
occur. Because the design includes two
RocketIOs that are looped back via FR4 on
the board in addition to the SMA breakout,
we repeated the test using the non-SMA loop-back. These tests yielded
substantially better results. In fact, the non-
SMA loop-back was capable of 3.125 Gbps
with identical payload and zero errors.
During these tests, we performed Time
Domain Reflectometry (TDR) on the
board as well, with results shown in
Figure 4. After reviewing these results, we
concluded that although the board
impedance was matched very well, a
severe impedance mismatch existed at the
SMA connectors.
This information suggested we should
look more closely at the layout, and we
determined that during the
design phase, a stub was overlooked.
As the FPGA and SMAs
both reside on the top (component)
side of the PCB, and the
traces are also on layer one (a 100
Ohm differential impedance
micro-strip), a stub is created at
the through-hole SMA.
Prior to a board spin, two
boards were used to test the theory.
Testing unmodified boards with
15 inches of FR4 (using an FR4
characterization board) yielded the
following results:
Board #1:
| | # of packets |
# byte errors |
| Test 1 | 0x10000 (65,536) | 136 |
| Test 2 | 0x10000 (65,536) | 306 |
Board #2:
| | # of packets |
# byte errors |
| Test 1 | 0x10000 (65,536) | 5527 |
| Test 2 | 0x10000 (65,536) | 8270 |
We modified the poorer performing
board by cutting the through-hole stub
protruding from the backside of the board
and grinding the stub flush with the backside
of the board.
With stubs cut, we observed the following
results:
Board #2:
| | # of packets |
# byte errors |
| Test 1 | 0x10000 (65,536) | 168 |
| Test 2 | 0x10000 (65,536) | 273 |
With stubs filed flush, we obtained the
following results:
Board #2:
| | # of packets |
# byte errors |
| Test 1 | 0x10000 (65,536) | 115 |
| Test 2 | 0x10000 (65,536) | 134 |
This seemed to be a promising
approach, so we decided to try another
option to eliminate the stub before doing a
re-layout of the board. The SMAs were
removed from board #2 and placed on the
backside of the board. This effectively
removed the stub, since the via and center
SMA conductor became part of the intended
transmission line.
Testing this modified board yielded zero
errors. This confirmed our finding that the stub was the cause of the unacceptable
error rate and that a layout change was
required to remove the stub.
Because we wanted to keep the SMAs
on the top side and minimize modification
to the existing microstrip, a board
spin was required. Noting the performance
of surface-mount SMAs in simulation,
we decided to proceed with a similar
SMA configuration for the board spin.
Revision of the Prototype Design
The prototype board was redesigned to
eliminate the stub by using a surface-mount
SMA connector. More extensive testing
would also be necessary to further verify the
operation of the new board design.
In addition to FR4 characterization,
we chose to use a more exhaustive test pattern
to validate the performance of the
new board. Furthermore, partial reconfiguration
would allow on-the-fly adjustments
to MGT parameters such as
pre-emphasis and differential swing. The
results are shown in Figure 5.
The test setup parameters were:
- MGT 4 connected through a 12-inch
RG 316 cable (Johnson 415-0029-012)
to a 20-inch FR4 trace on the Xilinx
MGT characterization board (Xilinx)
- Pre-emphasis at 25% (setting 2 of 0-3)
and differential swing of 600 mV
(setting 2 of 0-4)
- Test pattern is PRBS32 (using the Xilinx
BERT design)
- MGT 6 connected through 24-inch
RG316 (manufacturer unknown) to 15-inch FR4 characterization board (Xilinx)
- Pre-emphasis at 25% (setting 2 of 0-3)
and differential swing of 600 mV
(setting 2 of 0-4).
- Test pattern is PRBS32.
We ran the test until the 16550 UART
timed out (an evaluation-licensed core); the
total frames are shown in Figure 6. Note that
there are no errors; hence the bit error rate is
zero. Also, the error factor is defined on page
nine and table 2 in Xilinx Application Note
XAPP661 as the shortest gap between errors,
expressed in frames. Because
there are no errors, it makes
sense that this would be infinite.
The final TDR test results
are shown in Figure 7. A careful
reading of the results shows a
50% improvement over the previous
reading and confirms the
improvement of the new design.
Conclusion
During the design phase, you must be very
careful to identify all sources of trace and
stub length. In particular, watch for a mismatch
between your choice for throughhole
or surface-mount SMA devices and
the layout of your traces between the SMA
connector and the Virtex-II Pro FPGA. We
found it was easy to control the length and
impedance of the traces, but we overlooked
the impact SMA connector choice had on
the signal integrity.
Detailed design files and test measurements
are available with the purchase of an
Avnet Design Services Virtex-II Pro 3.125
Gbps Aurora Design Kit. You can order the
kit, part number ADS-XLX-V2PROEVLP7-6, for $599.
This design kit is just one of many available
to speed the development cycle for
complex processor, communications,
FPGA, DSP, and networking applications.
All of our design kits are modular and can
accept matching add-on modules, applications
software, design and debug tools, and
compatible IP cores. For more information,
visit www.avnetavenue.com.
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