Virtex-II Pro and Virtex-II Pro X FPGAs enable rapid development of flexible, serial backplane designs.

Historically, designers improved bandwidth performance in telecom, datacom, and computing systems backplanes by widening buses and increasing signal clock rates. Now, with data rates exceeding 622 Mbps and reaching the 1 to 10 Gbps range across 20 inches or more of backplane trace, passing data reliably over parallel buses is a challenge. Characteristics such as signal skew and loading – non-issues before – are suddenly problematic. Consequently, designers have shifted from parallel buses to more advanced serial interconnects.

However, even serial technologies have limitations, especially at data rates beyond the 1 Gbps level, where new problems arise. These limitations include reflections due to impedance mismatches along the signal path; signal attenuation from backplane materials; and added noise due to crosstalk and inter-symbol interference. Backplane designers should be aware of these issues and compensate accordingly to ensure that the bit error rate (BER), which is a measure of backplane robustness, is less than 10-12. This challenging task becomes even more critical as system throughput requirements approach 40 Gbps.

Fortunately, you can reduce the effects of the signal degradation phenomena by several means, including:

• Using better backplane material (FR4, Rogers)
• Using better connector types
• Improving layout trace to reduce the number of PCB layers and crosstalk
• Implementing different signaling schemes
• Using signal conditioning techniques.

Standards for Serial Backplanes
The large investment required to develop a proprietary serial backplane subsystem led to the organization of the PCI Industrial Computer Manufacturers Group (PICMG™), which develops open specifications for high-performance telecommunications and industrial computing backplane architectures.

PICMG recently produced a series of specifications (PICMG 3.x) called the Advanced Telecom Computing Architecture (ATCA™) for next-generation carrier-grade telecommunications equipment. ATCA features a new form factor and is based on switched fabric architectures, including dual star, dual-dual star, and mesh topologies. The base specification, PICMG 3.0, was adopted at the end of 2002. Additional specifications in the series include PICMG 3.1 for Ethernet fabric, PICMG 3.2 for Infiniband™, PICMG 3.3 for StarFabric™ Interconnect, and PICMG 3.4 for the PCI Express™ architecture.

Xilinx Solutions for Serial Backplanes
Xilinx has made significant strides in making serial technology available in our FPGAs and developing solutions such as IP cores, reference designs, and tools to help our customers gain the benefits of serial technology easily and quickly. Let’s take a look at the serial backplane solutions we offer.

Virtex-II Pro and Virtex-II Pro X
The Virtex-II Pro™ and Virtex-II Pro X family of FPGAs represent a high-end line of Xilinx FPGAs built on 130 nm, nine-layer copper and featuring an advanced fabric, embedded processors, and multigigabit SerDes devices. Both families are based on the same FPGA fabric, which provides abundant logic (as many as 125,000 logic cells), embedded memory (as much as 10 Mb block RAM), clock management, and DSP resources.

Standard SelectIO™ resources are also common, with as many as 1,200 user I/Os, 840 Mbps LVDS for interfaces such as 10 Gigabit Sixteen-Bit Interface (XSBI) and SerDes Framer Interface Level (SFI)-4, as well as XCITE (Xilinx Controlled Impedance Technology) on-chip termination.

Both devices also use the same embedded IBM™ PowerPC™ supporting 300 Mhz+ operation. The main difference is that the Virtex-II Pro FPGA has embedded RocketIO™ transceivers supporting speeds as high as 3.125 Gbps per channel, while the Virtex-II Pro X FPGA has embedded RocketIO X transceivers, providing up to 10.3125 Gbps per channel.

The largest of the 10-member Virtex-II Pro family of devices supports as many as 24 RocketIO transceivers. Each device can support operation from 622 Mbps to 3.125 Gbps, allowing up to 75 Gbps aggregate baud rate. Moreover, features such as programmable transmit pre-emphasis and output voltage enable the RocketIO transceiver to drive signals over 40" of FR4 material at 3.125 Gbps.

You can thus use RocketIO devices to address a number of emerging high-speed serial standards that fall within its range of operation, such as 1 Gigabit Ethernet, 10 Gigabit Ethernet (XAUI), PCI Express, Serial RapidIO, and Serial ATA.

RocketIO X transceivers found on Virtex-II Pro X FPGAs are capable of operating from 2.488 Gbps to 10.3125 Gbps. The larger of the two Virtex-II Pro X devices supports as many as 20 RocketIO X transceivers, providing an aggregate baud rate of more than 206 Gbps.

RocketIO X devices have the same features as RocketIO devices, as well as some additional features to improve signal integrity, such as receive equalization. With 10 Gbps capability, you can implement next-generation standard interfaces requiring serial 10 Gbps interfaces such as 10GBase-R Ethernet or SXI-5, or implement your own proprietary 10G interface.

Aurora
Aurora is a scalable, lightweight, link-layer protocol that you can use to move data across point-to-point serial links at baud rates as high as 75 Gbps. It is an open protocol that you can implement in any silicon device/technology. Aurora provides a transparent interface to the upper layers of proprietary or industry-standard protocols such as Ethernet or TCP/IP. This allows next-generation communication and computing system designers to achieve higher connectivity performance while preserving software infrastructure investments.

Mesh Technology on Xilinx
Mesh Technology on Xilinx (MTX) includes hardware and software reference designs and a bit error rate test (BERT) toolkit to enable rapid development of fullmesh serial backplane systems.

The PICMG 3.0 2.5G ATCA Development Platform is a reference board for PICMG 3.x line cards supporting port rates to 2.5 Gbps. The heart of the development platform is the Virtex-II Pro device, which serves as the interface to the full-mesh backplane.

Virtex-II Pro’s on-chip RocketIO MGTs allow all mesh cards on a full-mesh backplane to have direct, high-speed serial links to each other. The full-mesh card also allows application flexibility by reserving an area of the board for a pluggable “personality module” (PM). You can use the PM to implement any application-specific line card and easily connect to the fullmesh card through the included headers. PICMG 3.0 also specifies card and shelf management functionalities that are implemented in the development platform.

The Mesh Fabric Reference Design (MFRD) is a fully functional IP reference design that provides a building block for creating Virtex-II Pro-based mesh switch fabric interfaces. You can use the fabric reference design in a single Virtex-II Pro device or in several daisy-chained Virtex-II Pro devices, allowing up to 256 RocketIO serial channels. Figure 1 shows the concept of the mesh fabric interface and the daisy-chain scheme.

By having the flexibility to daisy-chain devices of different densities, you can choose an appropriate logic-to-RocketIO ratio. For example, more logic may be useful in a design where additional network processing functions are needed beyond those provided by an ASSP or ASIC. Flexible traffic scheduling is also possible with the support of as many as 16 priority levels and multiple scheduling algorithms on egress.

Figure 2 illustrates an example system with line cards that use the Virtex-II Pro FPGA and the full-mesh IP as the backplane interface.

GigaBERT is an IP toolkit that enables easy and comprehensive BERT of Virtex-II Pro-based, full-mesh fabric channels. Using GigaBERT, you can configure each RocketIO transceiver on each mesh fabric interface FPGA connected to a backplane as either a BERT tester or a far-end loopback. In effect, you can accomplish a scheme for simultaneous BERT testing of all links in a full-mesh fabric. Furthermore, GigaBERT’s flexibility enables you to quickly and easily create a BERT stress test to check for signal integrity in specific configurations.

Legacy Backplanes Support
Xilinx FPGAs are also ideal for customers who still need to support their differential or single-ended legacy bus architectures as they transition to serial architectures. For the highest performance differential solution, you can use the Virtex-II Pro or Virtex-II Pro X FPGAs to achieve LVDS rates as high as 840 Mbps. For low-cost LVDS, Spartan-3™ FPGAs support rates as high as 622 Mbps. Together, these devices provide a complete differential I/O solution with coverage of popular standards such as LVDS, Extended LVDS, Bus LVDS, Ultra LVDS, LVPECL, LDT, and RSDS.

For legacy designs using older singleended signaling standards, the Xilinx SelectIO technology available in Virtex-II Pro, Virtex-II Pro X, and Spartan-3 FPGAs allows the most comprehensive support for LVTTL, LVCMOS, PCI/PCIX, GTL, HSTL, and SSTL signaling standards. As a result, Virtex-II Pro, Virtex-II Pro X, and Spartan-3 FPGAs provide you with everything you need to support legacy backplane interfaces.

Conclusion
Designers of high-end telecom, datacom, and computing platforms have looked towards serial I/O technologies to address the increasing performance requirements of next-generation systems. Additionally, consortia such as the PICMG have stepped up to the plate to define serial backplane standards.

Whether proprietary or standardsbased, Virtex-II Pro and Virtex-II Pro X FPGAs with embedded multi-gigabit serial transceivers provide the technology to enable serial backplanes – including advanced, full-mesh architectures. Our growing portfolio of IP cores, reference designs, and toolkits for serial backplanes such as Aurora, Mesh Fabric IP, the PICMG ATCA Development Platform, and GigaBERT lead to shorter time to knowledge and ultimately shorter time to market. For more details about Xilinx solutions for serial backplanes, visit www.xilinx.com/esp/backplanes/.

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