The latest releases of ISE and ChipScope Pro design tools slash design and verification times while delivering the fastest performance available in PLD-based designs.

Xilinx Integrated Software Environment (ISE) 6.2i, the newest version of industryleading Xilinx logic design tools, is focused on delivering you the highest performance available in PLD design. With ISE 6.2i, Virtex-II Pro™ FPGAs are now on average 40% faster than the nearest delivering competitive FPGA offering. That’s up to three speed grades faster, and on silicon and software delivering today.

Spartan-3™ designers will also benefit significantly from using ISE 6.2i. You can improve performance by as much as 50% when using ISE 6.2i over our last release through a series of Spartan-3 enhancements:

• The Spartan-3 -4 speed grade has been enhanced to deliver higher performance
• The new, faster Spartan-3 -5 speed grade
• The clock-to-output performance has improved by 35-40%
• Embedded multiplier performance is as much as 50% faster – greater than 225 MHz
• ISE 6.2i now supports automatic local clock placement for Spartan-3 designs, delivering quicker and more accurate off-chip memory interface designs.

But faster performance has implications to all Xilinx customers, whether or not you’re currently attacking a high-speed project. High performance means that ISE will hit your design targets first, with fewer costly design iterations requiring you to tweak your code to meet timing.

Nearly Optimal Place and Route Results
Many design tools claim leadership, but ISE place and route (PAR) algorithms were recently tested by researchers from the University of California, Los Angeles (UCLA). These independent benchmark tests presented at the International Conference on Computer-Aided Design (ICCAD) showed that ISE PAR tools produce near-optimal timing-driven results. In an ICCAD paper titled “Optimality and Stability in Timing-Driven Placement Algorithms,” Microelectronics Center of North Carolina (MCNC) benchmarks demonstrated that ISE came between 8.3 and 4.1% of the optimal PAR solution.

“As part of our placement optimality study, we generated a set of placement benchmark examples with known optimal solutions. Our study showed the Xilinx place and route tools produced consistently near-optimal timing results on Virtex-II™ series devices,” said Dr. Jason Cong, a professor at the UCLA Computer Science Department and the faculty member directing the research. “We believe the excellent placement timing results were achieved by employing advanced timing-driven placement algorithms with efficient exploitation of the segmented routing architecture used in the Virtex-II series FPGAs.” This is the first time a quantitative timing optimality study has been reported on any FPGA placement and routing tools.

A Unique New Approach to Logic Debug
If you’re looking for a way to slash your verification cycle, you’ll want to see what’s new in the ChipScope™ Pro 6.2i release. The industry standard for realtime debug, the ChipScope Pro tool (along with Agilent Technologies’ new FPGA Dynamic Probe) combines to create a logic debug solution that can’t be matched by ASICs or competing FPGA solutions. ChipScope Pro can slash your verification cycle by as much as 50%, saving you significant time and money.

ChipScope Pro software lets you insert low-profile logic analyzer (ILA), bus analyzer (IBA), and Virtual I/O (VIO) software cores into your design or post-synthesis netlist. These cores allow you to view any internal signal or node within your FPGA, including the IBM™ CoreConnect processor local bus, on-chip peripheral bus for the IBM PowerPC™ 405 inside Virtex-II Pro Platform FGPAs, or the MicroBlaze™ soft processor core. Signals are captured at or near operating system speed, and brought out through the programming interface, freeing up pin assignments for your design. The ChipScope Pro logic analyzer can then analyze the captured signals (Figure 1).

ChipScope Pro and FPGA Dynamic Probe
ChipScope Pro software also links internal FPGA debug to your Agilent™ 16900, 1690, or 1680 series logic analyzer through the new ATC2 core. ATC2 synchronizes ChipScope Pro software to Agilent’s new FPGA Dynamic Probe technology, delivering the first integrated application for FPGA debug with logic analyzers.

This unique partnership between Xilinx and Agilent gives you deeper trace memory, faster clock speeds, and more trigger options, all using fewer pins on the FPGA. For more details on ATC2 and the FPGA Dynamic Probe, see Joel Woodward’s article, “The FPGA Dynamic Probe,” also in this issue of Xcell.

Conclusion
ISE 6.2i and ChipScope Pro 6.2i tools can help you realize lower project costs immediately. Release to release, Xilinx is committed to delivering higher performance and shorter implementation and verification cycles, helping you slash design times and lower your costs. With a performance advantage of as many as three speed grades, the slowest Virtex-II Pro device is still faster than the fastest competing FPGA in production, helping you save in device costs with the added potential to get more design into your target device.

Download the free 60-day ISE 6.2i evaluation at www.xilinx.com/ise_eval or the free 60-day ChipScope Pro 6.2i evaluation at www.xilinx.com/chipscope today.

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