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If you’re migrating from traditional bus
standards such as PCI and ATA to serialized
asynchronous architectures such as
PCI Express™ and ATA-2, you’ve probably
discovered that the tools for simulating
the designs and models for the various
buffers, connectors, transmission lines,
and vias have become more complex.
Although setup and hold, crosstalk and
single-ended delay are well understood,
accurately modeling these new parts and
their various complex behaviors adds to the
job’s complexity. To reduce the complexity
of interacting with model and design
parameters, Mentor Graphics and Xilinx
have jointly developed the RocketIO™
Design Kit for ICX™ software, producing
a design environment that allows you to
fully confirm what’s required to satisfy your
design specifications.
The Design Kit
The RocketIO Design Kit for ICX is a
companion to the standard Xilinx Signal
Integrity Simulation (Sis) Kit and comprises
a set of designs that match various Xilinx-supplied
SPICE transmission line
implementations. The kit is hierarchical, so
all of the different elements – such as documentation,
system configuration, simulation
models, and ICX databases – are
stored in different, relative location folders
within the ICX kit in the same parent
directory as the Xilinx Sis Kit.
The design kit enables easy simulation
analysis through the RocketIO menu and
through existing features of ICX products,
including eye-diagram, jitter, and intersymbol
interference analysis using predefined
and custom multi-bit stimuli with
lossy transmission line modeling.
Additionally, the IBIS 4.1 models,
which ICX uses for simulation, reference
the encrypted models supplied by Xilinx.
You can progress from design to design
through the kit’s environment, learning
more about the behavior of the RocketIO
buffers with each design or simulation,
such as what is achievable with these
buffers in a multi-gigabit channel and
what settings are required to maximize
system performance.
Standard Designs
The three standard designs supplied with
the RocketIO Design Kit include:
- Correlation
- Example
- Evaluation.
You can also verify your own design,
either in pre- or post-route states, in the
kit’s design area.
The Correlation Design
In a correlation design, the ICX database
reproduces the interconnect scheme
(Figure 1) from the Xilinx backplane example
and uses the same drivers and receiver
buffer models and parameters. The ICX
database provides virtual “push button”
operation so that you can run a signal
integrity simulation and compare the
resulting waveform with that provided in the Xilinx Rocket IO Design Kit in eyediagram
form. You can also verify that simulation
results match those supplied by
Xilinx with either the ICX self-contained
simulation environment using ADMS SI
or with HSPICE® as an external simulator
called from within ICX.
The Example Design
The example design has an expanded set of
transmission line examples to match the 10
examples that Xilinx supplies. Each of the
10 paths comprises a RocketIO transmitter
connected to a Teradyne™ HSD five-row
connector through two inches of differential
board traces; 16 inches of differential
board traces to a second Teradyne HSD
five-row connector; and finally two inches
of differential board traces from the second
Teradyne HSD five-row connector to a
RocketIO receiver.
The custom menu is more full-featured,
allowing direct simulation and eye
diagram display of any of the 10 pairs
from a single menu selection. The menu
also includes additional configuration
and pulse train dialogs that you can use to
change the simulation parameters, thus
allowing investigations of RocketIO
buffer behavior with these different settings
and stimuli.
In the example design, because the
transmission lines are fixed, you modify the
various settings of the buffer itself and then
conduct a simulation on whichever differential
channel you want to investigate.
The built-in RocketIO configuration
utility allows changes to the temperature
and pre-emphasis duration settings when
using the models directly from the Xilinx
IBIS writer utility. It also gives you additional
freedom to set the pre-emphasis
level, driver/receiver termination values,
and differential voltage swing when evaluating
other possible solutions.
To enable different bit-patterns and
speeds, you can also change the pulse train
from the standard 3.125 GHz to your own
specified pulse train using the pulse train
generator. This utility allows you to specify
bit patterns that can be used directly in
ICX or exported as an ASCII file, in either
SPICE PWL format or VHDL-AMS time
vectors, toggling between state
transitions.
The bit-patterns have an
underlying pulse duration over
which you can add jitter, where
the peak-to-peak value specifies
the six sigma points in picoseconds
of this Gaussian random
number. The pattern can be a
user-defined set of ones and zeros,
automatically defined as a random
number of user-defined pattern
length or as a pre-defined pattern.
Pre-defined pattern styles include
several pseudo-random bit
sequences and Fibre Channel
pulse trains (Figure 2).
The Evaluation Design
The evaluation design allows you
to load a pre-defined cross section
that matches one of the cross sections
from the example design. In
this virtual prototype environment,
you can place actual parts,
try “what-if ” routing, and see the
results in an eye diagram. As the
IBIS part models include other
buffers for Virtex-II Pro™
devices, you can simulate the
whole of the FPGA rather than
just the RocketIO channel.
This is where the channel’s
design is investigated in greater
detail, as you initially place the
devices to match your expected
end design rather than using a
fixed set of transmission lines. Using the
electrical editor functionality of the IS
floorplanner tool, you can add additional
parts such as connectors or terminators
and evaluate the impact of these on the
resulting eye diagram. When working
with these items, you can quickly determine
the result of the different preemphasis
settings. Additionally, you can
see the impact of different routing strategies,
including the fan-out pattern and
tightly or loosely coupled differential
pairs.
In the evaluation design, you can determine
how much pre-emphasis is required
to create the desired eye, as well as what
level of noise is introduced on adjacent signals,
on the board, or through the connector
due to that level of pre-emphasis. The
results of this virtual prototyping, as seen
in the eye diagram in Figure 3, can be
passed forward in the flow as constraints to
drive the electrical design, as well as placement
and routing examples.
Verification
The most advanced part of the kit allows
you to simulate your design or system. The
various parts of the system, backplane and
plug-in cards, or just a single card with onboard
channel, can be run through verification
using the same complex pulse trains
and model settings as before.
If required, you can modify
settings to improve channel
performance as measured by
the eye. You can also define
additional corner cases to evaluate
best- and worst-case scenarios,
including the impact of
one pair on the other in terms
of crosstalk; its impact on the
shape and size of the eye; and
the impact of other signals on
the channel.
Conclusion
Iteration happens in any
design process. The quicker
decisions can be made in
those iterations and the smaller
the impact on existing
design implementations, the
happier we all are.
The RocketIO Design Kit
for ICX allows you to make
initial evaluations of the technology
before any of the actual
design implementation has
occurred. As the design progresses
forward from initial
evaluations to the virtual prototype
environment, you can
confirm, in a pseudo-physical
implementation, that the
specifications can still be
achieved, or use the kit to
determine what changes are
required to achieve the desired
performance.
Finally, by verifying the placement, the
routing of the multi-gigabit channels, or
the whole design, you can confirm that
you are within specification. For more
information about the RocketIO Design
Kit for ICX, visit www.mentor.com/highspeed/resource/design_kits/icx-rocketio_designkit.html.
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