The Xilinx® Integrated Software Environment (ISE 6) is the current version of our industry-leading logic design tools, focused on delivering the highest performance available in PLD design. That leadingedge performance can help you get the highest quality of results available, and it can also significantly contribute to lowering design time and costs.

ISE 6 is packed with features designed to streamline the design flow, with technology such as:

• Timing-driven map – an ISE mapper option that helps pack more design into your highly utilized device
• ASIC-to-FPGA transition tools
• A spectrum of high-density design options built into ISE

Lower Potential Device Costs
Introduced in September 2003, ISE 6 adds a new timing-driven map option that helps get better design utilization for your FPGA device, particularly if the device is already more than 90% utilized. Timing-driven map is a next-generation enhancement to ISE physical synthesis, and combines placement with logic slice packing for Virtex-II™, Virtex-II Pro™, and Spartan-3™ devices to improve placement quality for “unrelated logic.”

In recent benchmarks, timing-driven map was tested on large, highly-utilized designs that contained tight timing constraints, versus the standard map and place and route flow. Results varied based on many factors in the design, yet timing-driven map showed an average 30% better overall logic placement.

This advantage gives Xilinx ISE 6 customers the potential to stay in their chosen device, even if utilization is pushing 90% or higher, when competing tools would have already forced the design into a larger and thus more expensive device. The timing-driven map option is included free with all configurations of ISE 6.

Streamlining ASIC-to-FPGA Transitions
The last few years have seen a steep decline in the number of ASIC design starts, and a good number of those projects have moved to Xilinx FPGAs for their logic delivery medium. Helping those project engineers transition from ASIC design flows with advanced support has been a priority for ISE development: thus, a number of tools are available to help.

Starting at the front of the design flow, you can use many of your existing ASIC code-checking tools to verify your HDL source. Xilinx has created a set of Xilinx FPGA-specific libraries for Synopsys™ LEDA VHDL and Verilog™ “linting” tools. The libraries are free to registered Synopsys users, and you can use them to configure your existing LEDA checker. They contain critical coding-style rules that help ensure HDL source quality and optimize implementation for the target FPGA.

ISE place and route tools also help you ensure efficient implementation. The place and route tools results offer interactive suggestions on how you can change your HDL code to reduce design size and implementation results. These suggestions help make more efficient use of FPGA resources and save overall design space.

The ISE design flow also supports technology that some ASIC designers have already invested in for verification. For example, formal verification is a technology that saw initial adoption in the ASIC design space. This structural equivalency comparison technique can drastically speed up verification time, and is often seen as an alternative to more traditional HDL simulation methods, particularly for higher density designs. These same tools also work with ISE FPGA-based designs, so if you’re using Synopsys Formality™ or Verplex Conformal LEC, you can use formal equivalency checking on your Xilinx FPGA design as well.

High-Density Design Techniques
You can also slash design times and project costs by using the high-density design options built into ISE. Free to all Xilinx users and included with ISE, these options can lead to faster timing closure and faster implementation times.

Area Mapping and Floorplanning
ISE includes two floorplanning options: PACE (Pin Assignment and Constraints Editor – shown in Figure 1), and ISE Floorplanner. Also, PlanAhead™, the high-level floorplanning tool, is now an optional, separately purchased Xilinx design tool offering through the recent acquisition of Hier Design, integrating directly to the ISE design flow.

These tools let you group logic together and associate those groups to an area on the target FPGA. Area mapping is a fast way to keep critical sections of the design together, associate HDL together by source such as purchased IP, or to efficiently reuse HDL from an earlier project. Good floorplanning can help achieve faster timing closure and optimize design performance.

Incremental Design
ISE also contains Incremental Design, a technology that can slash re-implementation time by as much as 75%. Incremental Design uses a design floorplan as the starting point. The design is then implemented or passed through the synthesis and place and route cycle. If subsequent modifications are required, Incremental Design updates only the area affected by the change, leaving the other completed design areas intact and dramatically shortening the re-implementation cycle. Incremental Design is useful during the verification phase, where debug and design changes are most commonly encountered.

Modular Design
Modular Design is another option included in ISE supporting the team design environment. Modular Design lets team managers divide a high-density design up into “modules.” Each design team can then use the entire suite of ISE design tools to complete their module independently. Modular Design deploys a “divide and conquer” strategy to highdensity designs, letting teams operate efficiently in parallel, finishing the overall project faster.

Conclusion
High-performance ISE technology isn’t only about getting the fastest clock speed in your design. The advanced technology built into ISE 6 also can cut your design and verification times, slash project costs, and offer potentially lower device savings in the long run. Upgrade your designs to ISE 6, or download the evaluation version of ISE by visiting www.xilinx.com/ise_eval/.

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