Embedded system development traditionally requires a hardware design cycle to create a prototype; a software implementation cycle can only begin once that prototype is available. Co-design and co-verification tools such as the Seamless™ co-verification environment (CVE) from Mentor Graphics provide great flexibility and early system integration, but these tools have mostly been used for large-scale systems such as ASIC designs. Ordinary embedded system designs have not yet benefited from hardware/software co-design and co-verification.

In recent years, innovations in FPGA technology have shifted the use of these devices from supporting logic to forming a central part of the embedded system. With their high logic density and high performance, modern FPGAs allow you to implement almost an entire embedded hardware system in a single FPGA device. Xilinx Spartan-II™, Spartan-3™, and Virtex-II™ Platform FPGAs (combined with the MicroBlaze™ soft processor core) and Virtex-II Pro™ Platform FPGAs (combined with the PowerPC™ 405 hard processor core) offer new hardware platforms and facilitate new methodologies in embedded system design.

The Nucleus™ real-time operating system (RTOS) from Accelerated Technology (Mentor Graphics’ Embedded Systems Division) fully supports Xilinx Platform FPGAs. Together with our FPGA design flow and Seamless CVE tools, the Nucleus RTOS is a complete hardware/software co-design and co-verification environment.

The Nucleus RTOS
Very few embedded software developers start their development on bare hardware; most choose a commercial embedded RTOS like Nucleus as the base environment and develop their applications on top of the operating system.

Generally, an RTOS provides a multitasking kernel and middleware components such as a TCP/IP stack, file system, or USB stack. Application developers build their application software by using the system services provided by the RTOS kernel and the middleware components. A number of commercial RTOSs are available: some have hard real-time kernels, some have extensive middleware support, and some have good development tools. The Nucleus RTOS has all of these features from a single vendor.

Figure 1 shows the Nucleus system architecture.

Nucleus PLUS
Nucleus PLUS, a fully preemptive and scalable kernel suitable for hard real-time applications, is designed specifically for embedded systems. It has a very small footprint; the kernel itself can be as small as 15-20 kB.

All Nucleus kernel functions are provided as libraries, so only the required kernel functionality is linked with the application code in the final image. Nucleus PLUS provides complete multi-tasking kernel functions, including task management, inter-task communication, intertask synchronization, memory management (MMU), and timer management. Recently, we added a dynamic download library (DDL) into Nucleus PLUS to allow dynamic downloading and allocation of system modules.

Nucleus Middleware
The middleware available for an RTOS has become an important factor when selecting a commercial RTOS for a particular application. As embedded applications become increasingly more complicated, application developers find implementing industry standards like TCP/IP, WiFi, USB, and MPEG more difficult. These standards are often implemented as middleware components and provided together with the RTOS.

The Nucleus RTOS has an extensive library of middleware support (Table 1), which covers every vertical market of the embedded industry. Nucleus NET utilizes a zero-copy mechanism for transferring data between user memory space and the TCP/IP stack, which significantly improves data transmission efficiency and reduces dynamic memory allocation.

Table 1 - Primary Nucleus middleware components

Nucleus Product	Function
Nucleus NET	Complete embedded TCP/IP stack
Nucleus Extended Protocols	Telnet, FTP, TFTP, Embedded Shell
Nucleus SNMP version 1,2,3	Network management protocols
Nucleus RMON (1-9 groups)	Network remote monitoring protocols
Nucleus Residential Gateway	NET, PPP, PPPoE, DHCP server
Nucleus WebServ	Embedded HTTPD web server
Nucleus EMAIL	POP3 and SMTP
Nucleus FILE	MS DOS compatible file system
Nucleus GRAFIX	Graphics-rendering engine with windowing toolkit
Nucleus USB	Complete USB stack for USB specifications 1.1, 2.0, and OTG
Nucleus 802.11 STA (WiFi)	802.11b and 802.11g protocol stack
Nucleus IPv6	IP version 6 protocol stack
CEE-J Java VM for Nucleus	CLDC, MIDP, Embedded Java, and Personal Java

Nucleus software fully supports the POSIX standard for software portability. POSIX interface libraries are available for all Nucleus middleware components.

Nucleus Device Drivers
The Nucleus RTOS has an extensive list of off-the-shelf device drivers. When you select a new hardware IP or peripheral to use in your design, the driver source code may already be available. If not, a driver template lets you easily develop a functional driver.

Mentor Graphics will continue to add device drivers to the Nucleus library for new hardware IP blocks for Xilinx FPGAs as well as for third parties, such as its own IP Division.

Nucleus Development Tools
The Nucleus RTOS has the most integrated development environment (IDE) in the industry. Combined with our Microtec compiler tools, the code|lab embedded development environment (EDE) and XRAY debuggers provide a complete software design flow, from compilation to debugging.

Our C/C++ source-level debuggers support both run-mode and freeze mode debugging with complete Nucleus kernel awareness. The XRAY debugger supports both homogeneous and heterogeneous multi-core debugging, and a wide range of processors and DSPs.

In addition to the Microtec compilers, the EDE, IDE, and debuggers are also integrated with many third-party compiler tools such as GNU.

For system-on-chip (SoC) users, integration of the Nucleus RTOS and XRAY debugger with other products in the Mentor Graphics lineup (such as Seamless CVE for hardware/software co-verification) offer a complete hardware/software co-design and co-verification platform.

Royalty-Free with Source Code
The royalty-free with source code business model of the Nucleus RTOS, combined with the high scalability and small footprint architecture, provides great value to customers developing large-volume products such as cell phones, PDAs, and cameras. A single up-front license fee covers all production rights for a single product using Nucleus software, with no additional royalty fees and no need to track shipment numbers.

Nucleus software has proven to be a robust RTOS and has been widely used in every vertical market of the embedded industry, including consumer electronics, telecom, defense/aerospace, automotive, and telematics.

Nucleus for Xilinx FPGAs
The scalable and configurable nature of Nucleus products, combined with the flexibility and versatility of FPGAs, provides great potential for hardware/software codesign, co-verification, and early integration of your software and hardware projects.

Nucleus for MicroBlaze
The MicroBlaze soft processor core features a Harvard-style RISC architecture with 32-bit instruction and data buses. A MicroBlaze soft core can be programmed into Spartan-II, Spartan-3, or Virtex-II Platform FPGAs.

Nucleus software fully supports the Xilinx MicroBlaze soft processor core with GNU compiler tool and GDB debugger.

Nucleus for Virtex-II Pro FPGAs/PowerPC 405
Many embedded system developers are already familiar with the PowerPC 405 processor. Xilinx Virtex-II Pro FPGAs provide fully configurable hardware platforms with the PowerPC 405 hard processor core.

Nucleus software fully supports Virtex-II Pro FPGAs with the PowerPC 405 hard core, providing a Microtec PowerPC compiler and XRAY kernelaware debugger, as well as GNU compiler tools and GDB debugger.

FPGA Reference Design for Nucleus Software
To give embedded system developers a quick start with Nucleus software for Xilinx FPGAs, we worked with Xilinx and Memec™ Insight to develop reference designs for running Nucleus software. Each reference design is a sample FPGA hardware configuration based on a Memec Insight FPGA development board.

You can build and implement all of the reference designs into the FPGA device by using Xilinx EDK and ISE software. For each reference design, we provide a Limited Version (LV) of our Nucleus software, including the Nucleus PLUS kernel and the relevant middleware (such as Nucleus NET) to help you evaluate Nucleus software with the FPGA.

The LV version of Nucleus software functions exactly the same as a full version, but is provided as binary only and runs for a limited time. Currently, we have FPGA reference designs for the following Memec Insight boards:

• Spartan-IIE LC MicroBlaze development board
• Spartan-3 LC MicroBlaze development board
• Spartan-3 MB MicroBlaze development board
• Virtex-II MB MicroBlaze development board
• Virtex-II Pro PowerPC development board

FPGA Design Flow
The FPGA reference designs for the Nucleus RTOS can be used as your starting point to build a custom FPGA-based hardware platform. All of the reference designs are provided as Xilinx Platform Studio (XPS) projects, so you can directly open these projects in XPS and edit, build, and implement the design with Xilinx EDK and ISE software. Typically, building a Nucleus system using an FPGA and configurable cores involves the following:

Configuring a hardware platform with FPGA, processor core, hardware IP, and memory
• Building the design with EDK/ISE software to generate an FPGA bitstream
• Building software libraries with EDK to generate low-level device driver code
• Developing Nucleus device drivers and Nucleus applications
• Programming the FPGA device
• Downloading Nucleus into the FPGA hardware board

Xilinx EDK and ISE software provide a complete environment for configuring and implementing an FPGA-based hardware platform. At the same time, EDK also generates software libraries and C header files for the hardware design. These libraries provide basic processor boot-up code and low-level hardware IP device driver function code. These low-level functions can be treated as a “BIOS” layer for Nucleus.

Figure 2 shows the source code directories generated by EDK in an XPS project. You will find one subdirectory for each piece of hardware IP, such as “emac_v1_00_d” for Ethernet and “uartlite_v1_00_b” for UART. Each subdirectory contains the driver code for that hardware IP. These driver functions are included with the hardware IP from the vendor and have been integrated into the EDK installation.

Nucleus software provides an OS adaptation layer that is an interface layer between the EDK-generated “BIOS” function layer and the Nucleus high-level device drivers. This OS adaptation layer serves as a hardware abstraction layer, which will significantly simplify the Nucleus device driver porting over FPGA-based hardware platforms.

Nucleus Software Debugging
Both MicroBlaze soft-core and PowerPC 405 hard-core designs provide a standard JTAG debug interface. So after implementing the hardware design in the FPGA, you can take full advantage of our JTAG-based code|lab EDE or XRAY debugger to facilitate application debugging. Both code|lab and XRAY have complete Nucleus kernel awareness, which can help you analyze complex real-time behaviors in a multi-tasking system.

Co-Design and Co-Verification
As we mentioned earlier, Nucleus software provides a viable platform for hardware/software co-design and co-verification. As one of the only EDA companies with an embedded software focus, Mentor Graphics’ Nucleus RTOS and XRAY debugger are fully integrated with our Seamless hardware/software co-verification software platform.

The combination of the Nucleus RTOS and Seamless co-verification tool provides you with one of the most comprehensive hardware/software co-design and co-verification tools possible.

Conclusion
Embedded systems are becoming increasingly complicated. To meet the challenge, integrated solutions including hardware/software co-design and co-verification are required. FPGAs with configurable processor cores bring a new, innovative approach to modern embedded system designs and open the door to hardware/software co-design and co-verification.

Nucleus software for FPGAs can significantly accelerate your hardware/software development cycle and improve your hardware/software integration quality. For more information, please visit www.acceleratedtechnology.com.

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