Managing signal assignment of high pin-count FPGAs, especially in multi-FPGA designs, is a growing problem. As most hardware managers will attest, this problem manifests itself in three ways.

First, the number of communication channels interfacing with a typical FPGA makes I/O assignment a cognitive challenge for logic designers to balance. These cognitive challenges include the handling of:

• Key constraints imposed by each channel, including voltage, signal strength, termination, and data versus clock skew.
• FPGA signal assignment constraints, such as I/O banking and simultaneous switching output rule sets.

Third, most of today’s EDA tools focus on solving the above issues for a single device, and have little or no knowledge of other system devices or their connections. The end result is a sub-optimal pinout that has been assigned without knowledge of the system. If you are a logic designer, you know it is likely that the pinout will need several refinements because of required negotiations between you, the hardware engineer, and SI engineer.

This time-consuming process is further exacerbated as system complexity increases, along with the need for precision change control and the resulting process management overhead. Figure 1 shows one of many complex design configurations.

Design F/X directly addresses these three core system design issues by:

• Significantly reducing the need to memorize I/O banking rules. DesignF/X provides an automated signal assignment optimization process and keeps you informed of DRC rules and requirements associated with your selected I/O standards.
• Providing system-level optimization of the signal assignment for one or more FPGAs and their associated devices in a PCB environment, while honoring the design rules. This optimization will result in the highest PCB routability, enabling you to reduce your design iterations and focus on core design.

We argue that the traditional design flow is a lengthy and error-prone process because:

• Several manual entry points exist, including HDL, signal assignment spreadsheets, schematic symbols, schematics, package drawings, and constraint information.
• There is no tool to validate data from package to component to netlist. For example, neither the schematic nor the netlist have knowledge of the package, yet package knowledge is required for proper validation.
• The back annotation process is often broken because required FPGA updates and attributes are not automatically passed completely through to the board tools for more efficient routing and planning.
• Generally, several iterations are required to get the correct FPGA pinout based on negotiations between layout engineers and FPGA designers.

You need not interrupt your current design flow, because DesignF/X provides several vector points at which you can analyze your design. DesignF/X also provides the I/O capabilities shown in Figure 3.

Only two successive steps are required to get an optimized design in a single iteration:

1. Create or import device pin assignment and board connectivity.
2. Analyze and optimize your configurable devices for the best possible routability while honoring Xilinx FPGA design rules.

• I/O banking DRCs (voltage, I/O standards, and on-chip termination are checked for intra-bank compatibility)
• Automatic reservation of Vref, VRP, and VRN pins when necessary, based on the selected I/O standard
• Automated recognition and handling of differential pairs, including swapping signals as a pair where legal during optimization

• Assign signals to pins and create signal groups and buses
• Apply I/O standards and mark specific pins as fixed if you do not want them considered for optimization

The screen shot for Figure 6 was generated after changing the I/O standard of two buses within the same bank. The output screen is interactive and shows which pins are causing the DRC error. A key ease-of-use feature shown is the way a number of related errors are summarized into one line.

After you have finished assigning signals, DesignF/X will perform one last DRC. If the DRC passes, you will be allowed to use the part for analysis and optimization on the “virtual PCB” screen. You can also rapidly generate a .ucf file for use in your Xilinx ISE environment for a rapid place and route check.

Signal Assignment for Optimal PCB Routing
Once you have all your programmable devices described and pin assignments defined, you can choose to import your connectivity information using a netlist file, or, if you do not have a netlist, use a table to define connectivity. Once connectivity information is defined, you can place your components on the “virtual PCB” and optimize them.

As a PCB designer you probably want to optimize your devices at the system level for the best possible routing early in the design phase – before completion of the FPGA place and route – while maintaining compliance to fundamental Xilinx DRCs on the I/O side. This will help you:

• Reduce PCB wire crossings, which directly correlates to reduced via counts, potentially reduced layer counts, and faster routes that enable early route studies for more what-if analyses
• Reduce SI complications and generate higher quality signals, also from reduced wire crossings and via counts (vias can result in stubs at high speed that are detrimental to edge rates)

The client faced the following challenges:

• A team co-located in three different crosscountry cities: the FPGA engineer, the hardware engineer, and the layout engineers were each located in different cities.
• The fast-paced design reached layout, but the PCB board was not routable.
• Obviously, any changes made to get the PCB board to route needed to comply with the rules of the Xilinx devices.

• The FPGA engineer sent the necessary Xilinx .pad files to the hardware engineer.
• The layout engineers sent the Cadence Allegro board file to the hardware engineer.
• The hardware engineer imported all files into DesignF/X and the PCB was optimizing within hours.
• The hardware engineer then output the updated Cadence Allegro board file and the updated Xilinx .ucf files and sent them back to the appropriate engineers.
• The FPGA engineer confirmed that the new pinouts for the Xilinx parts did not violate any Xilinx rules and signed off on the update.
• The layout engineers successfully routed the PCB board and back-annotated the changes to the Cadence OrCAD schematic.

Conclusion
Whether you are a logic designer, a hardware engineer, a PCB layout engineer, an engineering manager, or an FAE, you are likely facing one or more of the issues mentioned in this article with complex designs.

To learn about the latest DesignF/X features, visit the Product Acceleration website at www.prodacc.com. To schedule a DesignF/X demonstration, please send an e-mail to sales@prodacc.com or call (408) 551-0882.

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