Lowering total system costs is the key goal when developing high-volume/low-cost systems. Although many system designers carefully select components with the lowest unit cost, they often ignore the actual cost of manufacturing the PCB.

However, with careful design considerations, you can achieve the same functionality and performance within a smaller PCB, using fewer layers and sometimes with less components.

Some of the newer low-cost FPGAs, such as Xilinx® Spartan-3™ devices, now include a host of features that can reduce the number of on-board components and interconnect traces, enhance signal integrity, and reduce system electromagnetic interference (EMI) noise levels, essentially enabling you to significantly lower your system costs.

Reducing PCB Size and Complexity
The most obvious way to reduce the cost of any PCB is to make it smaller and have fewer layers. By reducing the total board area and using fewer layers (four instead of six, for example), you can cut down on the manufacturing expense.

For a typical 4” x 6” board, going from six to four layers can reduce the cost by anywhere from $2 to $4 per board. When you calculate the total savings based on the quantity of boards manufactured, this could be a substantial amount.

Another factor that influences the manufacturing cost of a PCB is EMI noise compliance. In cases where EMI is an issue, you need to design for the lowest possible EMI level, because trying to retrofit the PCB to meet EMI compliance can result in expensive redesign, re-layout, or shielding.

Good design techniques such as maintaining optimum signal integrity, having fewer traces running lower voltage levels, and distributing slower clocks on board can all help reduce the overall EMI level.

By using features found in Spartan-3 FPGAs, you can reduce total PCB manufacturing costs by optimizing the area and number of layers and minimize total EMI noise levels.

Spartan-3 Features
Digitally Controlled Impedance One of the key features provided by Spartan-3 devices is digitally controlled impedance (DCI). This allows you to not only (potentially) eliminate most external resistors, but also design for optimum signal integrity.

DCI actively adjusts both parallel and series terminations to accurately match the characteristic impedance of the transmission line. This adjustment process compensates for differences in I/O impedance that can result from normal variations in the ambient temperature, supply voltage, and manufacturing process. This feature is available for most popular I/O standards, including LVCMOS, LVDS, SSTL, HSTL, and GTL.

Figure 1 illustrates how the DCI feature can eliminate external resistors normally used for termination. Not only does this feature allow you to tune the output driver impedance – thereby optimizing signal integrity – but it also reduces the total number of components on board, with the resultant benefits in reliability, manufacturability, procurement costs, board area, and routability.

Drive Strength and Slew Rate Control
Another Spartan-3 feature is the ability to adjust the output drive strength and slew rate of the output drivers. Two options, fast and slow, control the output slew rate. You can select as many as seven different levels of current drive strength: 2, 4, 6, 8, 12, 16, and 24 mA. (These options are available when using one of the LVCMOS or LVTTL standards.)

Choosing the appropriate drive strength level is yet another means to minimize bus transients and optimize board signal integrity, as shown in Figure 2.

These adjustments can be made by merely updating the device bitstream and require no board re-layout. Thus, you can continue optimizing the drive strengths long after the board has been laid out.

On-Chip DCMs
All Spartan-3 devices have multiple high-performance digital clock managers (DCMs). Each DCM allows clock skew elimination, clock multiplication, clock division, and reconstruction, as well as phase shifting.

Although you can use the DCMs to eliminate the need for external clock management devices, they also allow you to run a slower clock on board (using the internal clock multiplication feature) and run fewer clock traces on board (using the clock reconstruction feature), as shown in Figure 3. Using these features simplifies the layout of high-speed PCBs and can lower overall EMI levels by allowing you to run fewer and slower clocks traces across the board.

On-Chip Voltage and I/O Standard Translation
All I/Os in Spartan-3 devices are allocated between eight banks, as shown in Figure 4. Each I/O bank has an independent VREF line.

The I/Os support most of the popular single-ended I/O standards such as LVTTL, LVCMOS, SSTL, HSTL, GTL, as well as differential I/O standards such as LVDS and RSDS. Because each I/O bank can independently support a different I/O standard and a different VCCO, this feature lets you implement voltage translators and I/O standard translators within the FPGA, eliminating the need for external components. Fewer components translates to smaller PCB and lower system costs.

Comprehensive Support for Differential Signaling
The Spartan-3 family is the only low-cost FPGA family whose I/Os support LVDS transmission without the need for external resistors. This popular standard is widely used for high-speed chip-to-chip communication because of its higher noise immunity, lower EMI, and higher performance.

Because LVDS is a low swing standard (~350 mV) with a slower slew rate (1V/ns), it exhibits lower EMI. And because it is a differential I/O standard, it has better noise immunity. LVDS allows for very high data transfer rates (622 Mbps in the Spartan-3 architecture), enabling fewer pins to transfer large amounts of data serially.

All of the device package combinations of Spartan-3 support LVDS. This means that you can choose low-cost QFP packages as well as higher pin-count BGA packages.

Figure 5 illustrates how competing lowcost FPGAs require three external resistors for each LVDS transmit channel. Spartan- 3 LVDS transmitters do not require the use of an external resistor network because the I/O buffers were designed to support low swing differential signaling.

Conclusion
Using the many features available with Spartan-3 FPGAs allows you to eliminate external components such as resistors, voltage translators, level shifters, and even external clock management devices. This not only increases board reliability and eases manufacturing costs, but also reduces the size of the board and may in some cases reduce the number of layers required for routing, potentially lowering total system costs.

If EMI compliance is a concern, there are many features within Spartan-3 devices that improve signal integrity, allow for fewer traces, and enable low swing I/O signaling ¡© all of which contribute to lower the EMI level of the system.

For more information on Spartan-3 features and how these features can help you reduce your system cost, visit www.xilinx.com/spartan3/.

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