The demands of next-generation wireless infrastructures require system designers to address not only processing bottlenecks but connectivity bottlenecks. Xilinx® FPGAs provide the ideal mix of high-performance DSP to handle the most demanding chiprate and radio algorithms and serial MGTs, addressing high-speed connectivity and interoperability challenges.

Tomorrow’s wireless infrastructure equipment designers will face an increase in algorithmic complexity and data rate brought on by the convergence of data, video, and voice. Solutions based on discrete devices such as microprocessors, DSPs, and transceivers provide tremendous headaches related to interoperability and latency, and can quickly drive up both cost and power per channel.

An FPGA-centric approach that combines Xilinx high-performance DSP capability and serial RapidIO™ (SRIO) will help alleviate some of these system performance bottlenecks and provide an integrated solution that better meets economic and energy constraints. In addition, an FPGA-centric approach allows you the flexibility to recover from mistakes and make hardware changes even after system deployment, thereby reducing overall design risk.

The DSP Industry Embraces SRIO
Figure 1 shows that in the late 1990s, GSM systems that provided voice communications only supported terminal data rates below 10 kbps. In contrast, W-CDMA systems, which started rolling out in 2002, needed to support voice, data, and video, and hence used 2 Mbps data rates. Future systems such as W-CDMA (HSDPA) and CDMA2000 (1xEV-DO and DV) will use data rates greater than 2 Mbps.

Designers have implemented ASICs – and more increasingly FPGAs – in wireless systems to handle digital radio (modulation/demodulation, DDC/DUC) and high chip-rate processing. FPGAs exploit parallel processing techniques through hard-wired embedded multipliers and provide you with the flexibility to make algorithmic changes even after system deployment, saving millions in maintenance or field upgrade costs.

Second, the need to transport such high information packets presents new connectivity challenges. Traditional buses are fast running out of bandwidth. Wide parallel buses are becoming too complicated to design and increasingly difficult to scale. As serial I/O technology begins to mature, wireless infrastructure equipment designers are looking towards system interconnect architectures based on MGTs to handle their transport problems. This gives rise to potential chip-to-chip and board-to-board interoperability headaches for system designers.

What is encouraging is that leading DSP IC suppliers that supply chip-rate and symbol-rate processing solutions (such as Texas Instruments™, Motorola™, and Xilinx) are at the forefront of the SRIO revolution and are keen to address connectivity and interoperability challenges in next-generation wireless infrastructure systems.

DSP processor vendors are projected not to start sampling products for some time, but as a system designer, you can start your development today using Xilinx Virtex-II Pro™ FPGAs, which incorporate high-performance DSP capability, SRIO connectivity, and even control functions through embedded PowerPC™ 405 processors.

As chip-rate processors, FPGAs provide an ideal complement to DSP processors, which have traditionally been used for lower sample- and symbol-rate processing. SRIO Benefits Using Virtex-II Pro FPGAs Serial RapidIO technology using Virtex-II Pro FPGAs provides a number of benefits to wireless infrastructure equipment designers:

• High-performance throughput provides the necessary bandwidth to cope with next-generation data transport needs.
• Lower complexity software and an ability to complete peer-to-peer transactions simplifies systems. In addition, it also provides a well-defined mechanism for congestion control.
• A flexible, low-risk solution offers scalable bandwidth options for future demands and fast time to market.
• With many DSP and other system IC (microprocessor, ASIC) vendors committing to SRIO, designers will have architectural flexibility. Virtex-II Pro FPGAs can provide interoperability security.
• Lower system cost through the use of a small silicon footprint and high bandwidth efficiency.

A more integrated option (shown in Figure 2), based on distributing the switching to multiple Virtex-II Pro devices that can also handle high-performance DSP for multi-channel radio and chip-rate processing, provides a more integrated, cost-effective approach.

Xilinx high-performance DSP capability lies at the heart of much of today’s second- and third-generation wireless infrastructure equipment. In addition to hundreds of 18 x 18 embedded multipliers for implementing custom algorithms, you can also use Xilinx DSP IP cores for demanding functions such as digital up/down conversion and forward error correction (such as 3GPP2 TCC, TPC decoding, and Viterbi decoding). You can find out more about the Xilinx XtremeDSP™ solution by visiting www.xilinx.com/dsp/.

Conclusion
With the addition of SRIO technology, Xilinx Virtex-II Pro FPGAs provide system designers with another means to further enhance system throughput, lower cost-per-channel, and retain the flexibility of an FPGA-centric solution.

Figure 3 shows that the Xilinx Serial RapidIO IP core provides a complete endpoint solution comprising transport, logical, and physical layers, and also complies with Revision 1.2 of the specification, including Errata 1. It supports all recovery mechanisms: packet retry, stomp, link request, and CRC.

For more information on the Xilinx Serial RapidIO core, visit www.xilinx.com/rapidio/.

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