If you are a DSP circuit designer, you should not feel restricted by the basic Xilinx logic blocks when building your design. Custom logic in a DSP circuit may not seem possible within the abstract world of Xilinx® System Generator, but on the contrary, you can easily realize custom logic by configuring a Xilinx MCode block.

A MATLAB® M-file from The MathWorks configures the block to emulate the algorithm realized in the file. You can attain custom control – and more specifically, state machines – with System Generator through configuration of a Xilinx black box, with code generated from Xilinx StateCAD. The VHDL code generated by StateCAD is emulated within the Xilinx black box block.

With advanced design and control logic, synchronization in DSP circuits also becomes an issue. You can realize handshaking (the exchange of control and status information between two blocks) in System Generator through delays and enable signals.

I would like to see Xilinx System Generator offer more flexibility (with the addition of output enables and other input parameters) to offer dynamic configuration of blocks. This flexibility comes at the expense of maintaining abstraction if you would prefer not to immerse yourself in the details of digital VLSI design.

Using a Xilinx MCode Block
If you are implementing a straightforward logic algorithm, configuring the MCode block is an easier solution than building the logic together through Xilinx blockset logic. Let’s describe an example implementation of custom logic; in this case, a switching circuit used in a filter. The algorithm in MCode is shown in Figure 1.

You must place the M-file in the same directory as The MathWorks Simulink® model file, followed by selection and placement of the MCode block in the model file. In the parameter listing for the MCode block, a MATLAB function parameter exists; here you would type “switch_cir” (the name of the M-file). The block will then configure itself and emulate the logic of the file, as shown in Figure 2.

Currently, the Xilinx MCode block cannot hold an internal state. But if you would like to implement a state machine (capable of holding an internal state), there are other alternatives, such as generating VHDL code to emulate the state machine and implementation through a Xilinx black box configuration.

Xilinx StateCAD Configuration
A simple state machine is given with the algorithm shown in Figure 3.

The requirements of the signal filter_ finish are described as follows: If the block is enabled, when the counter reaches the value of “BBRX_end,” filter_finish should go high and stay high until enable goes low. The state machine shown in Figure 4 was generated with StateCAD to emulate this logic.

Note that the default state in the VHDL code must be changed manually to “start.” This is because StateCAD’s default state in terms of VHDL code is that whose name is first alphabetically. Thus, to avoid complications, you should always create a default state in which to start called “aaa.”

You can then generate VHDL code (bbrx.vhd) for this state machine. The VHDL code can then be modified for configuration of a Xilinx black box. If a blank Xilinx black box is in a model file, and the VHDL code to configure it resides in the folder in which the model file is saved, then the configuration wizard for the black box will automatically generate an .m file to describe the functionality of the black box. With System Generator 3.1, you can configure the black box manually.

A problem exists when generating the .m file through the wizard. The configuration wizard for the black box cannot realize multiple entities in the .vhd file. The VHDL file bbrx.vhd contained multiple entities because of inefficient VHDL code generation through Xilinx StateCAD. Thus, you must manually manipulate the code to reduce it to one entity. You can then use the modified VHDL code in conjunction with the Xilinx black box wizard, creating a block shown like that in Figure 5.

System Generator 6.1 Features
The Fast Fourier Transform (FFT) implementation through configuration of a Xilinx black box block with M-file and VHDL wrapper file had problems in the past with execution in Simulink. These problems arose from the fact that System Generator did not appear to allow for multiple sampling rates (for instance, a clock and its respective down-sampled version).

This problem has since been alleviated with the addition of a clock enable probe system generator block. This block lets you effectively up- and down-sample a clock rate such that multiple clock rates are allowed within the same model. Figure 6 and Figure 7 illustrate an example of the clock enable probe.

DSP Circuitry Synchronization
Synchronous design goes hand in hand with the development of DSP circuitry. Therefore, it is important to be able to realize synchronous design in the high-level abstraction that System Generator provides.

Note that Xilinx delay blocks are used for “delaying” enable signals for a duration that matches computation effort time. You can use the output of this delay as an effective “output enable,” as shown in Figure 8. These delays are of such importance that before enabling the second block in a chain, you want to make sure the first block has completed its computation.

Exploring “FFT_power.mdl” demonstrates that latency requirements increase when the precision of the inputs and output of the multiplier block increase. Thus, the delays need to be modified when greater computational effort and thus greater time requirements in terms of Xilinx block latency result from overall design changes.

You could add greater flexibility to the Xilinx blockset with the addition of extra input parameters to some of the blocks in the set. For instance, the count-limited counter does not offer a count-to value as a possible input parameter. Therefore, dynamic configuration of the counter threshold is unrealizable.

Output enables allow one stage to signify it is complete, and thus for the next stage to start. Currently, most of the blocks in the blockset do not provide signals telling you when the block is finished its computation. This would be helpful in the handshaking for several Xilinx blocks.

However, you can realize output enable signals and counter threshold input signals by generating a VHDL file using the Xilinx Core Generator™ tool, and then configuring a Xilinx black box. But this requires more time from the designer and greater engineering effort as well.

We have to consider flexibility (the addition of output enables and other input parameters) to offer dynamic configuration of blocks versus a trade-off in maintaining the abstraction desired by DSP designers lacking strong digital design skills. It is therefore important to consider these ideas in future versions of System Generator.

Conclusion
A custom logic design may seem like a daunting task, but with the flexibility offered by Xilinx System Generator, it is quite achievable. Xilinx MCode and black box block configuration offer viable solutions for implementing custom logic.

System Generator is a very powerful and abstract tool, but we would like to see greater flexibility in terms of achieving synchronous design within System Generator.

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