Today, the role of FPGAs in the DSP market is well understood – there simply is no better way to create ultra-fast DSP applications. Yet combining these two technologies can be a challenge – DSP designers primarily use The MathWorks MATLAB™ or C/C++ to specify systems, whereas FPGA designers use VHDL or Verilog™. The only common approach between these two is that they often start with a block diagram.

DSP architects and FPGA designers have two completely different backgrounds, yet they must work together to create an optimum product. Their focus and expertise do not overlap, and as a result, they often have difficulty communicating. The team must verify that the FPGA implementation does indeed match the original specification given by the DSP architect, and usually they must modify the DSP algorithm to obtain the best possible implementation in the FPGA. This requires a constant exchange of information about simulation results, design size, design performance, DSP algorithm changes, and implementation results throughout the design process. Deciding on a single tool and a language that meets the requirements of the whole design team can be difficult, especially when budgets are low and turnaround times are short. What could be better than an environment understood by the entire team, using a single source code?

System Generator
Xilinx® System Generator is a system-level modeling tool that facilitates FPGA hardware design. It extends The MathWorks Simulink™ in many ways to provide a modeling environment well suited to hardware design.

The tool provides high-level abstractions that are automatically compiled into an FPGA at the push of a button. The tool also provides access to underlying FPGA resources through lower-level abstractions, allowing the construction of highly efficient FPGA designs. It is delivered along with a predefined Xilinx blockset library, but also allows access to other languages with which most FPGA designers are familiar. Finally, it offers the ability to design at a system level, and allows simulation, implementation, and verification within the same environment, usually without writing a single line of HDL code or even looking at the Xilinx ISE tools.

To highlight the System Generator design flow, we will use a Quadrature Amplitude Modulator (QAM) system design example (Figure 1), implemented according to the specifications provided by the Consultative Committee for Space Data Systems for telemetry channel coding specification (CCSDS 101.0 B-5).

Introduction to the QAM System Design Example
In our example, the overall QAM system starts with the transmitter. This subsystem accepts data from an input source, where forward error correction (FEC) is applied and an attached synchronization marker (ASM) is inserted into the data before modulation. The modulated data is then driven to the channel model, where inter-symbol interference, Doppler content, and additive white Gaussian noise are introduced into the signal. Finally, the receiver employs a 16-QAM demodulator that performs adaptive channel equalization and carrier recovery. The ASM is stripped from the demodulated data before applying error correction.

A PicoBlaze™ microcontroller controls the Reed-Solomon decoder, maintains frame alignment of the received packets, and performs periodic adjustments of the demapping QAM-16 quadrant reference. Both the transmitter and the receiver are targeted to the FPGA, whereas the channel is a Simulink model used for simulation and verification.

Although not all System Generator features are used in this design, it is a good example showing a combination of powerful features, using Xilinx blockset elements, legacy HDL code, a PicoBlaze processor, and hardware verification, resulting in a very elegant, efficient, and quick way to implement a complex design and qualify it in a single environment.

Design Implementation with System Generator
A System Generator design always starts and finishes with gateways to convert the Simulink double-precision data into a Xilinx fixed-point format. These gateways define the boundaries of your design; you can convert them into I/O ports for top-level designs or an I/O interface to import into a higher-level system. Between these gateways, you must use blocks from the Xilinx library blockset or import your own code through the black box interface.

The Xilinx blockset library comprises basic elements, math functions, DSP functions, communications blocks, control logic, and other useful elements. Each block is fully parameterizable, and a tight integration with the MATLAB workspace allows you to enter parameters based on complex equations or variables defined in the workspace.

Equations such as this one:

acc_nbits = ceil(log2(sum(abs(coef*2^coef_width_bp)))) + data_width + 1

This capability is only available with tools tightly integrated with MATLAB.

The Xilinx blockset library will not always meet your needs, and some functions are better suited for HDL implementation, such as complex state machines or complex legacy code. The System Generator black box allows you to bring VHDL, Verilog, and EDIF netlists into a design.

In the QAM design example, you can imagine replacing one of the FEC blocks (Reed-Solomon or Viterbi decoder) readily available from the Xilinx blockset library with your own HDL implementation through a black box. The black box behaves like other System Generator blocks – it is wired into designs, participates in simulations, and is compiled into hardware.

When System Generator compiles a black box, it automatically wires the imported module and associated files into the surrounding netlist. System Generator simulates black boxes by automatically launching an HDL simulator, generating additional HDL as needed (analogous to an HDL test bench), compiling HDL, scheduling simulation events, and handling the exchange of data between the Simulink and the HDL simulator. This is called “HDL co-simulation.”

At this point, you can also envision bringing MATLAB or C-code previously compiled with the appropriate MATLABto- gate and C-to-gate tools into the Xilinx black box.

Simulation and Verification
You can couple Simulink blocks with System Generator models to produce robust, flexible test bench environments. The convenience of this capability is that implementation and verification design phases can take place in the same environment. Such is the case with the QAM system design, where a mixture of Simulink and System Generator blocks were used to implement the design test bench.

This allows you to verify the functionality of your design at any critical probing points in a format well understood by the DSP architect (such as sinewave or constellation). You can also automatically generate this exact same test bench and export it to an HDL simulation tool, in this case in a format well understood by the FPGA designer (binary waveform). Also automatically generated is “golden data” confirming similar functionality in the Simulink and HDL environments.

In the QAM example, we chose to display the distorted channel on the output of the channel model (Figure 2) and the 16-point constellation on the output of the QAM demodulator (Figure 3).

Note that the automatic generation of the test bench and golden data saves an enormous amount of time over other design flows.

Proceeding with the design implementation, you can now generate the netlist through the System Generator token (Figure 4). At the push of a button, you can decide to generate a VHDL netlist, which will then have to be synthesized and place and routed, or you can decide to go straight to a bitstream or even target a hardware demonstration board.

Selecting hardware co-simulation makes it possible to incorporate a design running in an FPGA directly into a Simulink simulation. Hardware co-simulation compilation targets automatically create bitstreams and associate them with blocks. When the design is simulated in Simulink, results for the compiled portion are calculated in hardware. This allows the compiled portion to be tested in actual hardware, and can speed up simulation dramatically.

In addition to supporting specialized interfaces such as the XtremeDSP™ kit, System Generator provides a generic interface that uses JTAG and the Parallel Cable IV to communicate with FPGA hardware. This takes advantage of the ubiquity of JTAG to extend System Generator’s hardware- in-the-simulation-loop capability to numerous other FPGA platforms.

System Generator also allows you to run hardware co-simulation on your own development board. You can make design decisions and changes earlier in the design process and accelerate the design cycle directly from the Simulink environment.

Hardware Acceleration
The complexity and size of the QAM system resulted in lengthy simulation times. To accelerate the simulation and confirm the functionality of this system, the transmitter and the receiver were downloaded to two separate FPGA boards and brought back into Simulink using System Generator’s hardware co-simulation feature. You are now simulating an entire system from Simulink, with 10 to 100 times faster simulation time, instantaneously validating the functionality in the FPGA.

Interactively Control Hardware
You can also go one step further by accessing the FPGA while running the simulation. In this QAM example, the amount of Doppler content introduced by the channel can be controlled interactively during simulation; a slider bar shifts the carrier phase of the modulated signal (Figure 5). A significant adjustment to the slider invariably causes the receiver to lose lock. Interactive control over Doppler provides a simple yet powerful way to test the functionality of the receiver’s control systems.

Designers now have a simple way to simulate complex designs that require millions of samples that without hardware in the loop would take months to simulate. This, among other features, is something that only System Generator can offer. With other DSP design methodologies, you are required to verify designs in multiple design environments – a complicated process resulting in significantly slower simulation times.

Conclusion
System Generator is a mature tool that allows algorithm development, implementation, simulation, and verification in an environment understood by most designers. Although there are other design flows, no other tool offers features such as HDL co-simulation, hardware cosimulation, and integration with the ChipScope™ Pro tool and EDK, which are invaluable and only available in Xilinx System Generator for DSP.

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