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Home : Documentation : Xcell Journal Online : Article
Simplify FPGA Application Design with DIMEtalk



by Craig Sanderson, Systems Applications Engineer, Nallatech
c.sanderson@nallatech.com (9/15/04)


Remove the difficulties of system integration for single or multiple FPGA designs.
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Developing processing systems to implement high-performance applications is an extremely demanding task for engineers today. Increasingly, the demands of space, weight, and power have led designers away from traditional processor-based systems to FPGA-based solutions. This trend has led to significant advances in design flows, tools, and awareness of how to program FPGAs, which in turn has made developing the algorithmic portions of a design easier.

Designers must then begin to integrate the various elements of the overall system with one another and interface them to the outside world. In a microprocessor system this is generally simple, utilizing systemlevel libraries and operating system features. In an FPGA design flow it is generally much more complicated, especially if you are using more than one device.

Evidence suggests that developing this inter-process communications structure can consume as much as 80% of the development time on a typical project. This element of the design is generally not addressed by algorithmic design tools.

Having experienced first-hand how time-consuming implementing communications in FPGA applications can be, at Nallatech we looked for a way to make the process easier, developing design tools that we used internally for a few years. These early tools and principles formed the basis of DIMEtalk™, which is now available commercially.

DIMEtalk allows you to design custom inter-process communications networks within and between FPGAs at a conceptual level and automatically generate synthesizable FPGA code to represent them. This significantly reduces the time spent designing the communications element of an application, enabling you to concentrate your efforts on the parts of an application where your expertise lies, delivering solutions to customers faster.

System Communications
Developing applications to run in FPGAs has become easier, in part because of the advances made in design flows, tools, and general awareness of how to program FPGAs. Tools such as Xilinx® System Generator and other high-level implementation methodologies enable developers to quickly translate their algorithms from math-level functions into working FPGA algorithm blocks.

Once developed, connecting these algorithm blocks together is a complex and error-prone task. Even more complex is the connection of algorithms in multiple FPGA applications and the communication with external interfaces and backplanes.

This interconnectivity inside, the area outside and between FPGAs is termed “system communications” and can consume the vast majority of design time in many applications, distracting developers from their key expertise in the application being implemented. High-level algorithm design tools do not generally make provisions for implementation of system communications, so although the algorithm implementation has been made easier, system communications remains complex, error prone, and time consuming.

DIMEtalk: The Concept
Looking at the needs of FPGA application developers, we established key requirements for a system communications tool:

  • Scalability, catering to designs of all sizes and designs distributed across multiple FPGAs
  • Flexibility, tailored to the needs of the application
  • Easy algorithm interfacing, complementing algorithm implementation
  • Easy implementation, ideally through a software tool
  • Resource-friendly, minimizing hardware resource requirements
Looking beyond the FPGA world, the majority of data communications take place across some form of data network.

Data networks are appealing because of the flexibility and scalability they provide. When we developed the early DIMEtalk tool at Nallatech, we intended it to be primarily network-based for these reasons.

So in essence, DIMEtalk is networkbased and meets identified needs by providing:

  • A high-level software tool to enable users to develop communication networks
  • An intelligent packet-based network – routing tables automatically defined by software
  • Easy user node interfaces – block RAM, FIFO, memory map
  • Automatic FPGA-synthesizable code to represent the network
  • “Small footprint” network elements for efficient use of resources within Xilinx FPGAs
Physical Communications Infrastructure
We had to define the physical infrastructure of the tool – the network elements that would exist within the FPGA. We analyzed a number of data networking standards to assess their viability for use within FPGAs, but existing standards lacked the required flexibility and resource efficiency. For this reason, we developed a dedicated simplified network protocol and network infrastructure. The network elements used in DIMEtalk are as follows:
  • “Routers” direct data around the network
  • “Nodes” are the user interface to the network and can be connected to user application designs
  • “Bridges” move data between physical devices across a defined physical media (for example, between FPGAs)
  • “Edges” are used for protocol conversion to another data transfer standard (such as PCI, VME, or USB on Nallatech systems)
From a users’ perspective, nodes within the network are the most important; these are the points within the network where you connect your algorithm blocks. The available interfaces are block RAM, FIFO, and memory map-based, which makes developing compatible interfaces within algorithm blocks and connecting these to the network easy.

In runtime, packet-based transfers are used across the network, enabling the transfer of data between nodes within FPGAs and also to backplane interfaces and host systems. Because of the highly optimized network protocol and low overhead implementation used in DIMEtalk, the efficiency of data transfers is as high as 97%.

We are not suggesting that DIMEtalk networks should completely replace other types of data networks. However, within FPGAs and going between FPGAs on the same card, a low-resource, easy-to-implement network such as DIMEtalk makes sense – as demonstrated by the resource usage shown in Figure 1.

DIMEtalk is intended to be used alongside other data network and backplane types – that’s why the edge components are so important. The edges enable you to use low-resource DIMEtalk networks where it is right to do so and interface directly to other protocols off-card.

Using DIMEtalk
DIMEtalk is designed to make life easier for developers to deploy applications on an FPGA computing platform. The intuitive design flow shown in Figure 2 enables easy network implementation and you can use the design-entry tool of your choice for algorithm blocks. The stages of the design flow are:

  • Network Definition – conceptually design the network to provide communications links and interface points to algorithms as required across the FPGAs
  • Develop Algorithms – use HDL or other tools to develop algorithm blocks using HDL or other design flows connected to the interface nodes of the DIMEtalk network
  • Connect Algorithms – connect the completed algorithm blocks to the network; at this stage, the network and application are functionally complete
  • Assign to Devices – assign the whole design to FPGAs using a drag-anddrop feature
  • Code Generation – automatic code generation for design
  • Synthesis – using standard synthesis tools
  • Implementation – using the Xilinx ISE software tool flow
Application Architecture Example
Let’s look at DIMEtalk in an application context. The easiest approach is a very high-level one to avoid getting caught up in the details of a potential system – the focus being on the overall architecture rather than low-level functionality. A typical application might include the following:
  • VME form-factor
  • Multiple high-density platform FPGAs
  • High-speed external analog interfaces
  • High-speed synchronous SRAM memory
  • Gigabit Ethernet interface
This relatively complex hardware configuration is shown in Figure 3and Figure 4. In this case, the system comprises commercial off-the-shelf hardware products. From a functional perspective, the algorithm processing blocks that would perform the function of this application reside within the FPGAs. You can develop these algorithm blocks using the design entry flow of your choice, including HDL, commercial IP cores, and high-level languages and tools.

An example DIMEtalk network for this system is shown conceptually and in the DIMEtalk software tool in Figure 5 and Figure 6. The network spans across all five FPGAs in the system, with router and bridge elements in place as appropriate to enable the network to operate. Each FPGA has algorithm blocks(s) associated with it – these are connected to the network at user nodes. The user node type and location can be defined to fit your application requirements. In this example, the network is also connected through a DIMEtalk edge to the VMEbus host interface on the system – enabling direct data communications from the host to specific algorithm blocks inside the FPGAs.

What is clear from this example is the value DIMEtalk adds to the system. You can take an off-the-shelf system along with your algorithm blocks and rapidly connect all of these together and to the VMEbus.

Conclusion
Using DIMEtalk, you can efficiently implement the systems communications infrastructure required for FPGA computing applications. The generated network is flexible and provides a complete communications solution to connect together algorithm blocks, interfaces, backplane links, and host system. This type of infrastructure would have taken significantly longer to implement using traditional methods.

Forthcoming developments in future releases of DIMEtalk will include additional interface support and links directly into algorithm development tools, making application development even easier.

For further information about DIMEtalk, visit www.nallatech.com/dimetalk/.

Printable PDF version of this article with graphics. PDF logo (9/15/04) 358 KB

 
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