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Home : Documentation : Xcell Journal Online : Article
FPGAs Ensure Flexible and Adaptable IP Interconnection



by David Vant, VP of Marketing, Newport Networks
david.vant@newport-networks.com (9/15/04)


Newport Networks’ 1460 session controller enables direct IP-IP interconnection to support the full potential of IP services.
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IP transport has the potential to unlock an enormous variety of communication opportunities. Voice over Internet Protocol (VoIP) is just the first in an avalanche of powerful IP-based services. These will include sophisticated messaging; storefront and customer relationship management applications; and complex and personalized services for mobile workers, home workers, and “hot deskers.”

To secure the critical mass of subscribers that will allow this powerful new age to take off, IP network owners need a costeffective and flexible interconnect that will support the full diversity of IP services both now and in the future. Carrier-class robustness is also mandatory.

Newport Networks chose the Xilinx Virtex-II™ FPGA architecture to ensure those qualities in its next-generation IP-IP interconnect solution, the Newport Networks 1460 session controller.

Interconnecting IP Networks
The earliest all-IP networks relied on conventional public switched telephone network (PSTN) gateways to interconnect with other networks, even those with similar IP infrastructures. But a PSTN gateway cannot support cutting-edge IP services. Carriers will depend on these services to open new revenue streams, secure profitability, and differentiate their offerings. PSTN gateways are also quite expensive for making IP interconnections.

The Newport Networks 1460 session controller solves this challenge. It sits at the edge of the carrier network to enable service providers to interconnect at the IP level. Figure 1 shows how the 1460 supports an IP-IP interconnect, controlling signaling and media streams as they enter and exit the network. Benefits include broadband multimedia interconnection and lower peering costs.

Any solution designed to enable direct IP-IP interconnections must be extremely flexible. This flexibility will ensure maximum interoperability between network owners while IP standards and protocols continue to change quickly. Some protocols, such as the SIP (Session Initiation Protocol) family, are now quite well defined. Others are more esoteric and continue to evolve. And as some standards achieve de facto status, each new IP service seems to precipitate a flood of competing and complementary protocols. We expect the many IP standards to consolidate in the foreseeable future. Flexibility is therefore paramount.

Scalability must also be built into the infrastructure to support the subscriber growth that IP carriers are targeting. Easy management is also a prerequisite. This includes 99.999% availability, fully resilient operation, and the ability to modify key functions remotely and apply upgrades without powering down equipment. Further basic requirements of an IP-IP interconnect include features that preserve network security, ensure the availability of accounting information for accurate billing, and control Quality of Service (QoS) mapping and media translations.

Building the Next Generation
Choosing whether to implement the functions of a device like the 1460 session controller in software or hardware depends on the carrier’s business model and future plans. For example, you can bring a software-centric solution to market quickly, which is also very flexible. But drawbacks include a relative lack of scalability, and robustness also falls as subscriber numbers increase. These interconnects are also mission critical; because session controller servers are located in-line with the call parties, a software crash or other failure can result in dropped calls.

On the other hand, a number of off-the-shelf computing platforms are capable of supporting cutting-edge services for a reasonable number of subscribers. But they lack the robustness required of a true carrier-class solution.

For scalability and robustness, therefore, Newport Networks decided to implement a significant proportion of the functionality in custom hardware. But the new gateway also had to retain that crucial flexibility to remain protocol-agile and easy to manage – key attributes in delivering a low overall cost of ownership for IP carriers.

For a network to be easily managed, operators must be able to perform routine maintenance and apply periodic upgrades without visiting on-site to change cards, introduce additional logic, or implement hardware links to support test functions. In the IP world, new services emerge and evolve quickly, calling for frequent functional upgrades.

The imminent widespread adoption of Internet Protocol version 6 (IPv6) will also bring great implications for IP system flexibility. Adoption of IPv6 has already begun, predominantly by carriers in the Far East.

Standard Processing Hardware
Newport Networks has introduced the 1460 session controller to enable network operators to capitalize on the opportunities presented by the IP services revolution. At its heart are three distinct functional cards that perform line interfaces, application processing, and switching management functions, respectively.

Interestingly, a standard processing block is implemented on each card type. Around this hardware block, we can quickly configure a line interface card (LIC) by simply adding network processing blocks. The LIC processor performs header and packet stripping, packet analysis, traffic classification, and other processing. The session controller accommodates as many as 12 LICs, allowing easy scaling to support rapid subscriber growth. The Newport Networks 1460 is capable of supporting as many as 100,000 simultaneous, toll-quality VoIP calls.

Alternatively, by combining the processing core with switching blocks instead of network processing blocks, we can quickly configure a switching card. These are dual redundant cards that also include the switching fabric on board.

The processing hardware is implemented in an array of four PowerPC™ processors, each accompanied by high-performance FPGAs that deliver hardware acceleration and provide the flexibility to react to future changes in IP protocols, services, and business models. Hardware-accelerated functions implemented in the FPGAs include:

  • Data plane integrity checking and statistical gathering
  • Packet segmentation and reassembly on either side of the switch fabric
  • Checksum assist
  • Time-critical functions such as packet analysis are unloaded to the FPGAs.
The power of this configuration means that hardware assist, such as payload string search, is also an option.

Virtex-II Benefits
When looking for a suitable FPGA to take on these intensive processing tasks for the 1460 session controller cards, Newport Networks chose the Virtex-II FPGA. Valuable features include high I/O count, greater than 100 MHz bus speed operation, plentiful on-board RAM, digitally controlled impedance (DCI), and I/O banking. In particular, the internal RAM-based FIFOs enable a convenient software interface. This allows for smooth interaction between the PowerPC and the hardware-accelerated functions executed in the FPGA.

The Virtex-II on-chip delay-locked loop (DLL) circuits also proved useful for generating low-skew internal and external clock domains. These can be referenced to an incoming clock signal such as the common switch interface (CSIX), an open standard commonly used to interface a network processor with a physical switch fabric. The DLLs also allow output clocks to be phase-adjusted to meet setup and hold times for devices such as SDRAM. Virtex devices provide as many as eight fully digital dedicated DLLs on-chip.

Alongside the Virtex-II devices that add raw processing power, Xilinx XC9500 CPLDs perform MAC layer functions and other custom functions. These include proprietary data, control, and alarm interfaces to the backplane. The XC9500 CPLDs provide plenty of gates to implement these functions, with predictable routing and high I/O.

In the future, Newport Networks may move the 1460’s computing platform into the Virtex-II Pro™ architecture, subject to CPU bandwidth requirements. Virtex-II Pro FPGAs integrate PowerPC processing blocks directly on the chip, enabling cost and real estate savings and easing manufacturing demands.

Conclusion
The IP protocol environment is unlikely to settle down for some time. Quite apart from competition among protocols supporting IP services that we know of today, new IP-based services are quickly emerging. These are supported by legions of new protocols.

While the industry works toward greater standardization among the applicable protocols, equipment providers need to deliver solutions that have the power to meet today’s challenges as well as flexibility for the future. The Newport Networks 1460 session controller exploits the high-performance Virtex-II FPGA architecture to achieve each of these goals.

For more information about the Newport Networks 1460 session controller, visit www.newportnetworks.com.

Printable PDF version of this article with graphics. PDF logo (9/15/04) 485 KB

 
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