Today’s ASIC designers face a host of prototyping challenges. Most ASIC prototypes require the largest, most advanced FPGAs available, such as Xilinx® Virtex-4™ devices. Many are required to run at full speed, particularly for wireless designs. Therefore, timing quality-of-results (QoR) is critical. Plus, using incompatible synthesis solutions involves a time-consuming and error-prone manual effort to move designs between the ASIC and the prototype.

To address these challenges, Synopsys® has developed Design Compiler® FPGA (DC FPGA). DC FPGA brings the ASIC-strength synthesis technology of Design Compiler with new Adaptive Optimization™ (AO) technology to achieve excellent timing in fast run times. DC FPGA is part of a family of products that work in conjunction with Xilinx ISE to streamline the prototyping process – enabling you to design once.

Why Prototype?
The complexity associated with ASIC development has led to a significant increase in the number of design teams choosing to prototype their designs using an FPGA. According to Gary Smith of Gartner/Dataquest User Wants and Needs 2003, as well as our own surveys (as part of the Galaxy Technical Seminar), more than 40% of all ASIC designs have been prototyped in an FPGA. This trend is increasing over time.

Prototyping provides several benefits. Primarily, it offers a way to prove the design before undertaking an expensive ASIC manufacture. A physical prototype also enables the design to be rigorously verified using real data.

Industry analyst data gathered from the 2003 Synopsys Verification Seminar indicated that a majority (70%) of design re-spins still occur because of functional errors. Rapid verification of the programmable prototype can go a long way toward ensuring that the ASIC design is right the first time. Additionally, a prototype enables earlier integration of the complete system, providing a platform for software development that can continue in parallel with ASIC development and manufacturing.

The benefits of FPGA prototyping are clear – you will have more confidence in your design, which ultimately enables the development of a “right-first-time” ASIC in less time.

Prototyping Challenges
Ideally, the source register transfer language (RTL) for the design would be identical for both ASIC and FPGA. But in practice, you must make modifications to the RTL to get the best results from FPGA synthesis, or, in some cases, to even synthesize a design.

FPGA synthesis tools typically require you to write code in a certain style, following recommended coding guidelines, and each synthesis tool will have its own subset and variation of language support. Unless the ASIC and FPGA synthesis tools use the same compilers and directives, the RTL for the FPGA and ASIC implementations will likely be different.

Designers often use the Synopsys DesignWare® Library building blocks in the ASIC implementation of the design. Using a synthesis tool that does not support DesignWare requires you to write the specific elements yourself, which can potentially introduce errors in the design.

Meeting timing is often one of the most challenging issues in prototyping the design. Often designers are forced to use a fixed optimization strategy in traditional FPGA synthesis tools to try and meet timing. If the fixed method does not provide the required results, your only option is to make manual modifications to the RTL and try again – often with the same poor result.

These manual modifications are time consuming and error prone. They can lead to RTL “drift,” where the two descriptions become so diverse that the functional equivalence is jeopardized. Even small differences, such as a single signal being tied high or low in the FPGA, can spell disaster if carried through to ASIC manufacture.

The complexity of a typical design implemented in devices such as Virtex-4 FPGAs will almost certainly demand a team effort. Many existing tools restrict the design process to a top-down flow guided by a single user. FPGA designers want the flexibility to choose the design flow – just like their ASIC counterparts.

Although none of these flow differences in isolation represent an insurmountable challenge, collectively they can add up to a major overhead in the time and effort required to develop the prototype, affecting the design integrity between the FPGA and ASIC implementations. Unless you can easily migrate your design between FPGA and ASIC implementations, the benefits of prototyping are lost.

A Unified ASIC/FPGA Design Flow
Clearly, a common design flow that supports development of both ASIC and FPGA, without the manual intervention typical in the current approach to prototyping, would provide major advantages in ensuring design integrity and minimizing development time.

Design Compiler FPGA is an FPGA synthesis product intended for design teams who prototype ASICs using high-end FPGAs. DC FPGA is built on Design Compiler’s industryleading ASIC synthesis technology and is then customized to include FPGA-specific features. DC FPGA inherits DC’s reliability – proven through the development of more than 125,000 ASIC designs.

As shown in Figure 1, DC FPGA shares the same compilers, scripting language, and SDC (Synopsys Design Constraints) as Design Compiler. Because they use the same compilers, DC and DC FPGA will interpret the RTL the same way. This eliminates the manual changes in the RTL required when using different synthesis tools for FPGA and ASIC design.

Manually transforming gated clocks to the FPGA equivalent is not only very time consuming but also error prone. DC FPGA can automatically transform gated clocks in the ASIC design to the FPGA equivalent. This capability preserves clock gating functionality while improving timing and eliminates manual design modification. These features, along with full DesignWare Library building blocks support, allow you to easily migrate designs between ASIC and FPGA implementations.

To address the sheer complexity of today’s FPGA designs, DC FPGA supports top-down and bottom-up methodologies for team-based designs, enabling you to choose the appropriate methodology.

DC FPGA’s new AO technology automatically selects the best synthesis algorithm for the design. The algorithms are dynamically controlled given the nature of the design and the applied constraints. AO technology will also reorder the sequence in which the synthesis algorithms are run. The result is that AO technology provides the best timing in fast run times.

For designers who want even more flexibility, DC FPGA allows you to fully control the synthesis process on a block level. This level of control is very useful, particularly when you are trying to gain the last bit of performance from the design or want to carefully control the implementation.

Formal verification is a key part of a unified design flow because it mathematically proves that the RTL matches the implementation. DC FPGA supports formal verification with our Formality® solution. Both DC FPGA and Xilinx ISE output automatic setup files for Formality, which greatly simplifies the formal verification task. The formal verification flow with Formality is shown in Figure 2.

Conclusion
The goal of effective prototyping is to have your design up and running at the desired speed with the least possible effort, while maintaining design integrity with the ASIC implementation.

DC FPGA will help you reach this goal. With DC FPGA, you can use common RTL for both the FPGA and the ASIC implementations to maintain design integrity, allowing you to design once. The timing performance of DC FPGA with AO technology, combined with the flexibility in synthesis, will help you meet your most difficult design challenges, getting to prototype quickly.

DC FPGA is just part of the complete ASIC-strength prototyping solution from Synopsys. Other tools supported in the Xilinx flow are Formality for formal verification, DesignWare Library IP, Leda® for RTL design and code checking, PrimeTime® for static timing analysis, VCS® for simulation, Module Compiler™ for datapath synthesis, and HSPICE® for analysis of multi-gigabit serial I/Os.

Although it is a new product, DC FPGA has a rapidly growing base of more than 80 customers. For more information about Design Compiler FPGA, visit www.synopsys.com/products/dcfpga/dcfpga.html.

“As a customer-centric designer and manufacturer of microprocessors, flash memory devices, and systemon- chip solutions for the computer and communications industry, AMD is pushing the speed limits of today’s FPGA device technology. Using DC FPGA from Synopsys, we were able to meet the 40 MHz wireless LAN 802.11g ASIC prototyping chip performance target – a significant speed increase over what we were able to achieve with other FPGA synthesis tools. DC FPGA’s compatibility with Design Compiler and the flexibility to run on a Linux™-based platform significantly accelerates our design flow process by giving us access to a common design environment for both ASIC and FPGA design.” – Dirk Haentzschel, Sr. Design Engineer, AMD Dresden Design Center

“Design Compiler FPGA impressed us because it was the only FPGA synthesis solution that had a working formal verification flow. In addition, DC FPGA was able to handle gated-clock transformations that are critical for our low-power mobile products, as well as a 23% timing improvement over our existing FPGA synthesis solution.” – Dr. Michiel Lotter, Co-Founder and VP of Engineering, Zyray Wireless

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