Using in-depth market knowledge, Barco designs and develops solutions for largescreen visualization, display solutions for lifecritical applications, and systems for visual inspection. Barco is currently active in the traffic, surveillance, broadcasting, presentation, simulation and virtual reality, edutainment, events, media, digital cinema, air traffic control, defense and security, medical imaging, avionics, and textile industries.

My particular division at Barco, BarcoView Command & Control in Belgium, has been a Xilinx® customer for just over two years. Our division’s choice to standardize on Virtex™ products was based on the availability of the embedded PowerPC™ processor, first introduced by Xilinx in their Virtex-II Pro™ product family.

We like to design with FPGAs in our systems because they can be reprogrammed throughout the life of the product. This critical feature allows us to add features from one generation to the next without having to redesign the whole system.

BarcoView Command & Control is working on a rugged family of LCD monitors. These products are designed for rough environments where commercial display products would not survive. In these designs, FPGAs are mainly tasked to perform video and image processing.

The system is currently designed around a Virtex-II Pro device, in which the PowerPC processor, running a real-time embedded operating system, controls the complete display system. Looking at the new features of the Virtex-4™ FX family, we are planning to migrate these Virtex-II Pro designs that use the PowerPC processor to Virtex-4 FX devices in a future version of the project.

Besides the central control of the display system, we also use FPGAs in the data path for specific processing. The part of the design where we chose to implement the Virtex-4 FPGA is an optional feature of the displays, where it performs real-time image scaling on the video stream.

This scaler module can receive a video stream on its input at a very high rate (160 MHz x 24 bits = 3.84 Gbps), perform scaling on the stream, and send out the scaled stream at the same rate. With the amount of data being processed and because of the way the scaler algorithm works, we must store the incoming video stream into memory before processing it. Thus, we had to look at very fast external memories (DDR2).

Memory Interfaces Made Easy
When searching for the right product for our application, we looked at many alternatives. However, it rapidly became clear that Virtex-4 devices could best perform the required tasks.

The main reason for choosing Virtex-4 FPGAs was the availability of the ChipSync™ feature, with support for DDR-2 400 memories. Having support for DDR-2 400 gives us enough bandwidth to reduce the number of physical RAM chips needed, reduce the board real estate, and in the end reduce system cost.

Looking at the data flow, these video streams are digitized into pixels up to 24-bit RGB (it could be a narrower stream depending on the input source). The incoming stream is stored into an input memory buffer at a frequency reaching up to 160 MHz. The data from this input memory buffer is then fed to the scaler core, also on 24 bits, at a maximum frequency of 100 MHz.

After the core has processed the data, the video stream is written back into an output memory buffer at 100 MHz on 24 bits. The output memory buffer can then be read at a frequency reaching 160 MHz on 24 bits to further process the data. After all that processing and some more, the images are displayed on the LCD monitor.

As shown in Figure 1, which represents the Virtex-4 LX15 ecosystem of our design, the memory bandwidth requirements for the input and output buffers are identical. Focusing on the input memory stream, we can see that the bandwidth required is (160 MHz + 100 MHz) * 24 bits = 6,240 Mbps.

This is where the advantages of 400 Mbps DDR-2 are realized. Because of this memory speed, we can select a 16-bit-wide DDR-2 SDRAM running at 200 MHz and still have enough bandwidth to process the input memory buffer streams (the stream coming from the input source and the stream going to the scaler core).

A simple calculation shows that 200 MHz x 2 (double data rate) x 16 bit = 6,400 Mbps. This is higher than the 6,240 Mbps previously calculated for the input buffer. Of course, we need to take into account a small overhead for the memory controller (during transients), but the margin should be more than enough to guarantee reliable system operation. If for any reason the controller’s overhead becomes such that we cannot guarantee that the system would work properly, we can always lower the 100 MHz core frequency.

ChipSync technology allows us to easily reach 400 Mbps and intuitively design this interface. Without this feature, we would have needed a 32-bit interface to the external memory. Though running at half the clock rate, more physical SDRAM on the board would be required, as there is no such thing as a small SDRAM device. In addition to the higher unused memory locations, we would have required a larger package for the scaler device because of the increased number of pins, using more board real estate.

ChipSync technology also allows us to easily use DDR-2 interfaces, enabling us to choose the very latest in SDRAM technology. This helps to avoid obsolescence issues, a common problem in the memory industry.

Block RAM: Not Just Memory
Another critical point when choosing the right FPGA is the amount of block RAM available in the device. Having flexible, fast internal RAM is a critical factor for us because we use block RAM for two things: as video line memory and as FIFOs for the DDR-2 memory controller. Smaller, slower, or less flexible RAM blocks would have produced a more complex DDR-2 memory controller design, resulting in larger logic requirements and therefore a larger device.

In addition to speed, flexibility, and size, the integrated FIFO logic available on each block RAM allows us to save a substantial amount of logic and guarantees fast FIFO operation, simplifying the design of our whole system.

Conclusion
The logic savings obtained through the use of the integrated FIFO, ChipSync technology, and the use of smaller external memories results in a significant cost reduction. Additionally, the ease of use, implementation, and modification brought by the hard IP blocks makes the Virtex-4 LX15 device perfect for this application.

After designing with the Virtex-4 LX FPGA, we are looking forward to evaluating the Virtex-4 FX platform to see how we can benefit from all the new features available with the integrated PowerPC processor. For more information about Barco and our products, visit www.barco.com.

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