The debate over FPGAs as a viable alternative to ASICs and ASSPs has been ongoing for nearly a decade. Industry analysts iSupply, Gartner Dataquest™, and others have documented the trend in decreasing ASIC design starts and the increase in FPGA design starts.

Next-generation platform FPGA devices based on 90 nm have greatly expanded high-performance processing and system integration options. They continue to push ASIC design starts lower as additional application solutions are defined.

With the beginning of the new millennium, the debate continued with the introduction of Xilinx® Virtex-II™ and Virtex-II Pro™ devices – the industry’s first platform FPGAs. These high-performance devices, with their flexible device integration capability, programmable I/O, and significantly lower overall design cost, helped to usher in and establish SoC design methodology and quickly assumed innumerable ASIC SoC designs.

The addition of high-performance RISC CPUs, block RAM, multi-gigabit high-speed serial I/Os, dedicated DSP functions, and other system enhancements introduced technological advances that further solidified the rise of platform FPGAs over their ASIC SoC counterparts. However, to get high-performance DSP, processing, or connectivity features for a specific applications domain, designers were typically forced to purchase the largest, costliest devices. The larger parts had the biggest helpings of advanced features, while the smaller parts had reduced portions of the same.

Today, a new breed of domainoptimized, mullti-platform FPGAs from Xilinx – the Virtex-4™ family – promises multi-dimensional application scaling based on required features and cost goals. By combining the economic benefits of an innovative columnar architectural approach with advances in process technology (90 nm/300 mm), Xilinx is poised to move beyond the $5.1 billion programmable logic market to capture additional share in the $84 billion ASIC and ASSP markets (Source: Gartner Dataquest 2007).

Just the Right Mix
Based on the revolutionary Advanced Silicon Modular Block (ASMBL) columnar architectural approach, Xilinx can now cost-effectively develop multiple FPGA platforms, each with different combinations of feature sets. Thus, a specific platform can be optimized specifically for a certain domain of applications – such as logic, DSP, connectivity, and embedded processing – to meet application requirements previously delivered only by ASICs, ASSPs, and similar devices, while remaining programmable at heart.

Not only does the designer or design team have a choice in selecting the ideal platform, they also have a choice in choosing the device size with just the right feature mix to best achieve needed capability and performance at the lowest possible cost.

This unique flexibility and ability to create optimal application domain subsystems sets even higher standards for FPGAs. Devices that are both hardware- and software-programmable enable more flexible implementation options than either ASIC or ASSP devices. Reinvestigating, changing, or enhancing system architecture at any time in the development process provides the ultimate tool kit to meet application requirements.

Designers can use this same capability to evolve hardware in the field to meet new requirements or avoid expensive hardware upgrades. This flexibility becomes paramount given today’s many emerging and competing standards.

The “Total Cost” Advantage
FPGAs have demonstrated a clear and consistent trend in reducing cost and making FPGA technology more suitable for a wider range of applications. The combination of 90 nm silicon fabrication technology with 300 mm wafers results in a cumulative effect: increasing the number die-per-wafer five times over previous devices. Increasing the die-per-wafer together with architectural integration enables substantially lower system costs.

A key and often overlooked component in favor of programmable logic’s economic advantage is clearly demonstrated in how technology is used throughout the world. No two people use the same technology, systems, or software, nor do they subscribe to or want the same content.

Higher costs and longer design times for ASICs and ASSPs relegate their primary uses to proven lower-risk, very-high-volume applications. The rapid and significant increase in ASIC development costs clearly gives the advantage to platform FPGAs in today’s leading-edge applications. The overall cost benefit of zero NRE pushes the high-volume ASIC or ASSP crossover point upwards, locking in FPGAs like never before.

Conclusion
Domain-optimized multi-platform FPGAs are revolutionary in their ability to accelerate the deployment of FPGA technology into many more application areas. The combined leverages of reduced risk, dramatically shorter design cycles, and zero NRE will soon move all but the highest volume applications away from cell-based ASIC implementation toward more flexible, forgiving architectures like today’s domain-optimized FPGAs. For more information, visit www.xilinx.com/virtex4/.

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