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Configuration memory in Xilinx®
Virtex™ FPGAs is used primarily to
implement user logic, connectivity, and
I/Os, but it is also used for other purposes.
For example, it specifies a variety of static
conditions in the two functional blocks,
DCMs and RocketIO™ multi-gigabit
transceivers (MGTs).
Sometimes an application requires a
change in the conditions of the functional
blocks while the blocks are operational.
You can accomplish this through the global
internal configuration access port
(ICAP) or through partial dynamic reconfiguration,
using JTAG or SelectMap in the
“persist” mode.
Since the late 1990s, all Virtex FPGAs
have supported this powerful dynamic partial
reconfiguration feature. However, partial
dynamic reconfiguration required you to
have a detailed knowledge of the configuration
logic functions, the configuration registers,
and the location of configuration bits.
DRP Functionality
The new Virtex-4™ dynamic reconfiguration
port (DRP) is an integral part of
the two functional blocks, as it simplifies
the dynamic reconfiguration process
greatly. These configuration ports exist in
the DCMs and RocketIO MGTs.
In this article, we’ll describe the
addressable, parallel write/read configuration
memory implemented in each functional
block that permits reconfiguration.
This memory has the following attributes:
- It is directly accessible from the
FPGA fabric. Configuration bits can
be written to and/or read from
depending on their function.
- Each bit of memory is initialized with
the value of the corresponding configuration
memory bit in the bitstream.
Memory bits can also be
changed later using the ICAP.
- The output of each memory bit
drives the functional block logic, so
the content of this memory determines
the configuration of the functional
block.
The address space can include status
(read-only) and function enables (writeonly).
Read-only and write-only operations
can also share the same address
space. Figure 1 shows how the bitstream
configuration bits drive the logic in functional
blocks and how the reconfiguration
logic changes the flow to read or write the
configuration bits.
Figure 1 also lists each signal on the
FPGA fabric port. Individual functional
blocks can implement all or only a subset
of these signals. In general, it is a synchronous
parallel-memory port, with separate
read and write buses similar to the
block RAM interface. Bus bits are numbered
from least significant to most significant,
starting at 0. All signals are
active high.
Synchronous timing for the port is
provided by the DCLK input, and all the
other input signals are registered in the
functional block on the rising edge of
DCLK. Input (write) data to the functional
blocks is presented simultaneously
with the write address and DWE and
DEN signals before the next positive edge
of DCLK.
The port asserts DRDY for one clock
cycle when it is ready to accept more data.
The timing requirements relative to
DCLK for all the other signals are the
same. The output data is not registered in
the functional blocks. Output (read) data
is available after some cycles following the
cycle that DEN and DADDR are asserted.
The availability of output data is indicated
by the assertion of DRDY.
DRP Implementation in DCMs and MGTs
As mentioned earlier, the DRP is available
in two major Virtex-4 functional blocks.
Writing a specific value to a specific
address will manipulate configuration bits
and alter functions or attributes on the fly.
The user and configuration guides
describe the address space (locations) and
allowed values for each function.
In the DCM, the DRP allows you to
make dynamic adjustments to the phase
shift value of the digital phase shifter
(DPS) and to change the multiply (M)
and divide (D) values of the digital frequency
synthesizer (DFS). A new primitive,
DCM_ADV, has been added to the software tools to show the additional DPR
signals. For example, writing a 04h to
address 50h will change the M value to 5.
In the MGTs, the DRP allows
advanced users to manipulate many
attributes of the physical media attachment
(PMA) and the physical coding
sublayer (PCS). The new signals are part
of the regular MGT primitive and can be
operated by the application. The MGT
implementation makes a large number of
settings available for you to change
dynamically. Various comma detect,
channel bonding, and other attributes
can be manipulated.
Conclusion
The Virtex-4 dynamic reconfiguration
port provides an easy-to-use, block RAM-style
interface that empowers you to
modify the functionality of your application
while the device is operating. This
leads to flexible implementations and an
application that can adapt to changing
conditions – without having to reconfigure
an FPGA with a different bitstream
from scratch.
For more information, see the configuration
guide, www.xilinx.com/bvdocs/
userguides/ug071.pdf.
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