As FPGAs grow in size, quality on-chip clock distribution becomes increasingly important. Clock skew and clock delay impact device performance; managing clock skews and delays with conventional clock trees becomes more difficult in larger devices.

Xilinx® Virtex-4™ devices solve this challenge by providing as many as 20 fully dedicated on-chip digital clock management (DCM) circuits. DCM provides zero propagation delay and – along with fully differential global clock trees – low clock skew between output clock signals distributed throughout the device.

Each DCM can drive up to 12 of the 32 global clock routing networks within the device. The global clock distribution network minimizes clock skews due to loading differences. By monitoring a sample of the DCM output clock, the delay locked loop (DLL) compensates for the delay on the routing network, effectively eliminating the delay from the external input port to the individual clock loads within the device.

In addition to providing zero delay with respect to a user source clock, DCM provides multiple phases of the source clock. The DLL can act as a clock doubler or divide the user source clock by up to 16. DCM can also act as a clock mirror. By driving DCM output off-chip and back in again, you can use it to de-skew a boardlevel clock between multiple devices.

Digital Phase Shift (DPS)
Virtex-4 FPGAs provide a digital phase shift (DPS) module that phase shifts the DCM’s output clock in small increments – 1/256th of its period. You can operate the versatile DPS in four different modes for maximum flexibility: fixed, variable-positive, variable-center, and direct.

Digital Frequency Synthesis (DFS)
The DCM digital frequency synthesis (DFS) module provides two outputs, CLKFX and CLKFX180, derived from the input clock by frequency multiplication and division. Through a frequency calculator, you provide the multiply and divide values implemented by the DFS module. For example, an M value of 19 and a D value of 8 yields a 2.375 source clock multiplier.

DCM Features
DCMs are located in the center column of the Virtex-4 architecture. This enables well-matched clock routes to and from every DCM for enhanced symmetry.

The Virtex-4 DCM’s superior performance does not just include a wider operating range. It encompasses lower jitter, improved phase accuracy, finer phase-shift resolution, tolerance of imperfect clocks and board designs, less duty-cycle distortion, and less sensitivity to sporadic voltage changes. Xilinx also added new features. You now have the choice to trade off a wider phase shift range versus higher frequencies.

In addition, a new function in the Virtex-4 architecture is the dynamic reconfiguration port (DRP). The DRP allows you to directly access some features in DCM through a block RAM-style interface. You can directly phase shift the delay line elements and change M and D values.

The software view of DCM has changed as well. Three Virtex-4 primitives – DCM_BASE, DCM_PS, and DCM_ADV – offer progressive features to enhance your design choices.

Xilinx also added a new DCM companion block, the phase-matched clock divider (PMCD), to the Virtex-4 family. Let’s discuss the clock management features of these new clock resources.

Phase-Matched Divided Clocks
PMCDs create as many as four frequencydivided and phase-matched versions of an input clock, CLKA. The output clocks are a function of the input clock frequency: divided-by-1 (CLKA1), divided-by-2 (CLKA1D2), divided-by-4 (CLKA1D4), and divided-by-8 (CLKA1D8). CLKA1, CLKA1D2, CLKA1D4, and CLKA1D8 output clocks are rising-edge aligned to each other, but not to the input (CLKA). Figure 1 illustrates the new PMCD primitive.

Phase-Matched Delay Clocks
PMCDs preserve edge alignments, phase relations, or skews between the CLKA input clock and other PMCD input clocks. Three additional inputs (CLKB, CLKC, and CLKD) and three corresponding delayed outputs (CLKB1, CLKC1, and CLKD1) are available. The same delay is inserted to CLKA, CLKB, CLKC, and CLKD; thus, the delayed CLKA1, CLKB1, CLKC1, and CLKD1 outputs maintain edge alignments, phase relationships, or the skews of their respective inputs.

You can use PMCDs alone or with other clock resources, including global buffers and DCMs. Together, these clock resources provide flexibility in managing complex clock networks.

The PMCDs are located in the center column right next to the DCMs. They are grouped as pairs in each tile.

Conclusion
The many features and functions of the clock management subsystem allow you to maximize system performance. By taking advantage of DCM to remove on-chip clock delay, you can greatly simplify and improve system-level designs involving high fan-out, high-performance clocks. Virtex-4 devices have an abundance of clock management resources along with comprehensive software support.

Specialized individual features further improve the ability to optimize design performance. Frequency synthesis is a powerful feature to generate a wide range of frequencies in the FPGA or the entire system. A fine-resolution phase-shift capability allows you to improve margins. And the new PMCD further increases the number of clock derivatives that can be generated without the use of additional DCMs.

For more information, see the user guide at www.xilinx.com/bvdocs/userguides/ug070.pdf.

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