The advanced silicon features introduced with Xilinx® Virtex-4™ FPGAs are readily available through ISE™ (Integrated Software Environment) 6.3i technology. This latest release of Xilinx design software comes ready to deliver maximum design performance, with new features and optional tools that will speed your Virtex-4 project to completion.

Advanced Timing Closure and Performance
ISE software lets you get the most out of Virtex-4 devices and your target project. Benchmark testing on a suite of real-world, customer-based designs demonstrates that Virtex-4 FPGAs, with ISE 6.3i design software, are as much as 43% faster than the nearest competitive FPGA. On average, that’s an extra speed grade advantage.

The performance-driven ISE technology – like our exclusive timing-driven map option – helps you achieve better design packing and better performance, particularly if your target device is already more than 90% utilized. Timing-driven map can yield 30% better overall design performance depending on design utilization.

This additional performance advantage gives you the potential to stay in a lower density target Virtex-4 device, even if utilization is pushing 90% or higher, when competing tools would have already forced the design into a larger, more expensive device.

High-Density Design
ISE design software also includes a full spectrum of tools for larger density designs, including area and logic group floorplanning, incremental design for faster design recompile cycles, and modular design for team-based project approaches. High-density designers can also separately purchase the new PlanAhead™ hierarchical flooplanner, which wraps all of these methodologies into one separate advanced tool. Together, these tools augment the design flow of highdensity projects with methodologies that speed through to project completion, as well as performance-locking strategies to help bring large designs under control.

Area Groups
Using either PACE (Pinout and Area Constraints Editor) or ISE Floorplanner, both included with all configurations of ISE design software, you can quickly floorplan areas of logic from your design onto your target Virtex-4 device. You can create area groups around hierarchical HDL boundaries, or let PACE create default area estimates for target logic, or draw logic areas by hand.

Visualizing the different areas of logic helps you partition out areas for design reuse or IP placement, or section off where the “tough” areas of the design will be concentrated. Most importantly, area planning can help accelerate timing closure by grouping critical logic and paths together, and minimize the number of interface points between modules.

Modular Design
ISE design software also includes modular design, a capability that implements a “divide and conquer” strategy for large designs – and for the corporate environments that deploy teams of engineers to tackle them. A design team manager first plans the design project, using floorplanning to partition the overall larger project into smaller design “modules.” These modules can then be assigned to individual team members for completion independent of the other modules.

Completion is focused on only that particular module of the overall design, with all teams completing their work in parallel.

Once a module is finished, its place and route results are locked while the project manager waits for the remaining modules to be completed.

Modular design delivers full planning control over the larger design, implementing a true bottoms-up design approach that completes the larger project much faster.

Incremental Design
Incremental design, also included with ISE design software, combines the quick-andeasy facet of area groups with the performance-locking aspects of modular design to deliver faster runtimes during heavy design iteration cycles.

Using PACE, you can assign area groups along hierarchical HDL boundaries; the overall design is then completed as usual. Should an incremental change become necessary, incremental design guarantees that you only have to re-implement the logic area that needs to change. The remainder of the design stays locked and intact, drastically speeding up overall compile times.

Incremental design also lets you make full use of the verification phase by delivering much faster overall project compile times. You can tweak critical design areas or implement ECO design changes late in the cycle with minimal impact on the larger FPGA project.

PlanAhead
In June 2004, Xilinx announced the acquisition of the leading-edge PlanAhead hierarchical floorplanner, developed originally by Hier Design. The PlanAhead floorplanner is a separately purchased tool option to the ISE design flow that is ideal for Virtex-4 high-density designs.

The PlanAhead tool utilizes an ASIC-style floorplanning methodology using a block-based approach. It enables you to analyze, detect, and correct potential implementation problems earlier in the design cycle, leading to the following benefits:

• Quicker incremental design changes
• Faster place and route
• Greater consistency and predictability in place and route
• Fewer design iterations
• Improved design performance
• Tighter utilization control
• Reuse of intellectual property and teamwork

You can also lock placement results for individual blocks that already meet timing so that subsequent place and route iterations do not change their performance, further stabilizing the overall design and making the overall results more consistently predictable. The PlanAhead tool wraps area groups, incremental design, and modular design into a single ASIC-strength floorplanner. Figure 1 shows Virtex-4 floorplanning using the PlanAhead hierarchical floorplanner.

Speed the Design Flow – ISE Architecture Wizards
The architecture wizards are a series of menus and dialog boxes built into all ISE configurations. These graphical menus let you quickly set advanced configuration parameters for FPGA silicon features. The wizards then write out editable VHDL or Verilog™ source code that is instantiated directly into your target project.

For example, the clocking wizard lets you easily set clock frequency, phase, multiplier factors, and delay for Virtex-4 devices and other Xilinx FPGAs using DCMs (digital clock managers). With the architecture wizards, you can rapidly set up and program advanced FPGA features, so even novice users can learn the most advanced Virtex-4 capabilities quickly.

Also new in ISE 6.3i software are two Virtex-4-exclusive architecture wizards, the ChipSync™ and XtremeDSP™ slice wizards. The ChipSync wizard configures groups of I/O blocks into an interface for use in memory, networking, or other types of bus interface design. You can quickly define key parameters such as the width and I/O standard of the data, address, clocks/strobes, clock buffers, and data bus specifications. All information is then presented in a clear and concise table for review.

The XtremeDSP slice wizard, shown in Figure 2, provides easy control of the revolutionary Virtex-4 XtremeDSP slice technology. This new silicon capability lets you build high-performance DSP filters and custom pre or post-co-processing DSP algorithms. The XtremeDSP slice wizard lets you specify accumulator, adder/subtractor, multiplier, or multiplier and adder/accumulator DSP modes. You can graphically set input and output bus data widths, pipelining options, clock enable, and reset pin setups, and then review parameters and output the results as HDL-ready code.

50% Faster Verification Cycles
Verification is one of the most timeconsuming and time-critical phases of the design flow. As with most logic design suites, HDL verification and timing analysis are available. The ISE tools also link to additional verification technologies unique in FPGA design, including formal equivalency verification through Formality from Synopsys™ and Prover eCheck from Prover Technology AB, making quick work of verifying Virtex-4 high-density designs.

The ISE design tools also link directly to our optional, separately purchased ChipScope Pro™ real-time debug environment. ChipScope Pro tools insert lowprofile logic analyzer, bus analyzer, and virtual I/O software cores during design capture. These cores are then synthesized and implemented into your silicon, allowing you to view:

• Any internal signal within the FPGA
• Embedded processor signals, including the IBM™ CoreConnect processor local bus or on-chip peripheral bus supporting the PowerPC™ 405 inside Virtex-4 FX family devices
• Embedded processor signals for the MicroBlaze™ soft-processor core

The ChipScope Pro environment also links internal FPGA debug to Agilent Technologies™ bench-top logic analzyers using the included ChipScope Pro ATC2 core. This core synchronizes the ChipScope Pro tool with Agilent’s FPGA Dynamic Probe software.

This unique partnership between Xilinx and Agilent delivers deeper trace memory, faster clock speeds, and more trigger options, all using fewer pins on the FPGA, making Virtex-4 design debug as much as 50% faster than other logic verification methodologies.

Conclusion
You can unlock the power of Virtex-4 FPGAs with the ISE 6.3i FPGA environment, the most complete available for programmable systems design. Whether your design includes DSP, embedded, and highspeed serial I/O design, Xilinx ISE software and our optional System Generator for DSP, ChipScope Pro, and EDK and Platform Studio products will get your Virtex-4 LX, SX, and FX designs running with the maximum performance, while shortening design cycles and getting you to market faster.

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