Ethernet is the predominant wired connectivity standard. The range of standard products for Ethernet is large, and it just got bigger with the introduction of the Xilinx® Virtex-4™ FX device family. Combining embedded Ethernet connectivity with the unique flexibility of the Virtex-4 feature set, Xilinx has created a compelling single-chip platform for solutions not possible with existing off-the-shelf products.

The Virtex-4 FX device family contains paired embedded Ethernet media access controllers (MAC) that are independently configurable to meet all common Ethernet system connectivity needs. Each Virtex-4 FX device contains either two or four MAC, implemented using Xilinx IP immersion technology, as shown in Figure 1.

Using standard Xilinx design products, you now have the unprecedented capability to create a huge range of customized packet processing and network end-point products for 10/100/1000 Mbps Ethernet.

An external physical layer device (PHY) is required for the MAC to connect to a network. The Virtex-4 FX device directly supports all standard serial and parallel PHY interfaces for both copper and optical Ethernet connections. In addition, Virtex-4 embedded RocketIO multi-gigabit transceivers can be used to drive Ethernet directly across PCB traces, such as serial backplanes, for in-system connectivity. PHY connections can be routed to any user pin or RocketIO block in the device.

In this article, we'll review the feature set of the embedded Ethernet MAC blocks in Virtex-4 FX devices, and offer some pointers on how you can start right away using them with standard Xilinx design tools, LogiCORE™ IP, and development boards.

Feature Set
The Virtex-4 Ethernet MAC addresses all common configuration requirements for embedded Ethernet connectivity, and is fully compliant to the IEEE802.3-2002 specification. It will allow you to build Ethernet systems that support VLAN, jumbo frames, and end-to-end flow control.

Built-in hardware address filtering reduces the burden on software of processing unneeded frames. You can independently configure each MAC for multiple rates and topologies:

• 10 Mbps or 100 Mbps full- and halfduplex
• 10/100 Mbps full- and half-duplex
• 1000 Mbps full-duplex
• 10/100/1000 Mbps full-duplex

Connecting the MAC to external PHY and optical modules is supported through the PHY interface to the FPGA fabric. This provides flexible use models for the MAC, allowing, for example, attachment to a shared processor bus or to custom packet processing hardware.

Controlling the MAC in your system is performed through the host interface, which provides flexible software access to the internal registers. Each MAC pair shares a common host interface, which can be directly accessed by the embedded PowerPC™ 405 device control register (DCR) bus, or from the FPGA fabric. Let’s describe each of these interfaces in more detail.

PHY Interfaces
Your application will require connection to a particular medium – copper, fiber optics, or one of your own invention. The PHY interface provides many options to meet your requirements.

All common interfaces to external media are directly supported in the PHY interface. As the PHY interface is routed to the outside world through FPGA fabric, creating “bump-in-the-wire” solutions in FPGA fabric is straightforward. PHY interfaces fall into two categories: one using SelectIO™ resources and another using RocketIO serial transceivers.

The first category is typically used to connect to a discrete external PHY:

• Media independent interface (MII) for 10/100 Mbps
• Gigabit MII (GMII), and reduced GMII (RGMII) for 10/100/1000 Mbps

• Serial GMII (SGMII) for 10/100/1000 Mbps
• 1000BaseX for 1000 Mbps

A MII management (MIIM) interface is also included, which allows your software to access external PHY registers through this standard IEEE interface. The registers are accessed via the address map in the host interface.

Host Interface
For your software to control the MAC, a host interface provides access to the internal registers. A dedicated DCR bus connects the embedded PowerPC directly to the host interface, requiring no additional FPGA resources. Alternatively, the host interface can also be accessed directly from the fabric, providing a flexible solution for porting legacy driver software. Each pair of MAC shares a single host interface.

The registers accessed through the host interface are used by driver software to initialize and control the MAC during operation. All register values may be preset at power-on from the FPGA fabric. This allows the MAC to be used by applications that do not include a processor and software.

The registers provide access to the following settings:

• Independent receiver settings for reset and enable, pause frame address, jumbo and VLAN frame enables, half/full duplex, and passing frame check sequence (FCS) to the client
• Independent transmitter settings for reset and enable, inter-frame gap (IFG) adjustment, jumbo and VLAN frame enables, half/full duplex, and FCS from client
• Independent flow control enables for receiver and transmitter
• RGMII/SGMII status, and speed for fixed and negotiated settings
• Management interface enable and clock rate
• Receive-side address filter access – unicast and multi-cast address entries

Client Interface
Ethernet frames are passed between the MAC and your design across the client interface, which is divided into receive and transmit sides.

Receiver Side Client Interface
On the receive interface, frame errors and unmatched frames are signaled to the user logic. When flow control is enabled, any valid pause frames received will be flagged as invalid.

Transmitter Side Client Interface
The transmit interface will indicate collisions on half-duplex connections, and will corrupt a truncated frame in the case of FIFO starvation in the middle of a frame. When flow control is enabled, the transmitter interface will automatically assert back pressure on the client when a pause request frame is received from the remote host.

Flow Control and Statistics Vectors
A separate flow control interface allows the client to make pause requests to the far end, allowing the pause interval to be set for each individual request. Separate interfaces provide separate statistics vectors for the receiver and transmitter portions of the MAC. The IEEE-defined statistics are updated on a per-frame basis, and can be accumulated using circuitry in the FPGA fabric.

Over-Speed Operation
This feature allows you to clock the MAC at higher rates than allowed by the standard. The double-width interface on the client side means that your design can process frames at the same system frequency as normal operation, but at twice the data width, providing up to 2 Gbps in each direction.

Virtex-4 Ethernet MAC Use Models
The features described previously provide the Virtex-4 Ethernet MAC with multiple use models. Some examples of these are given here, but this should not be considered a complete list.

• Attach the MAC to CoreConnect PLB or OPB peripheral interface in FPGA fabric to embedded PowerPC or MicroBlaze™ processors, as in Figure 2.
• Create a custom interface to packet processing hardware implemented in FPGA fabric, such as protocol offload, DMA engines, embedded FIFO, and embedded block RAM. Figure 3 shows an example scheme for a Transmission Control Protocol (TCP) offload engine (TOE), and/or Remote Direct Memory Access (RDMA), as covered by the iWARP protocols from the RDMA Consortium.
• Directly connect multiple MAC blocks to Virtex-4 embedded FIFO and external QDR and DDR memory for classification, policing, and switching applications, see Figure 3.
• Provide independent packet monitoring and statistics collection, using custom hardware in FPGA fabric that connects directly to the statistics interface of the MAC blocks.

• Optical gigabit Ethernet connectivity – connect directly to external optical modules through the Virtex-4 RocketIO transceiver for 1000BaseX operation (Figure 4)
• 10/100 Ethernet connected to external copper PHY through RMII interface implemented between the MII PHY interface and SelectIO pins
• 10/100/1000 tri-mode Ethernet to external PHY or SFP module through SGMII connection to RocketIO transceiver, utilizing a RocketIO block

Tools, IP, and Development Boards
Xilinx provides support for the MAC with tools, LogiCORE IP, reference designs, and Virtex-4 development boards.

Virtex-4 Embedded EMAC Wrappers
Available from the Xilinx CORE Generator™ tool, you can automatically generate HDL wrappers for the MAC instantiations in your design and completely configure the MAC through the GUI. A low-level software driver for the embedded PowerPC to access the MAC across the dedicated DCR interface will also be automatically generated.

Embedded Developers Kit (EDK)
The EDK tool enables you to build a complete processor subsystem around the MAC. The tool includes standard Xilinx LogiCORE IP to connect the MAC as a CoreConnect peripheral, and will automatically generate a software driver.

Xilinx Ethernet LogiCORE IP and Reference Designs
Much of the legacy Virtex-II Pro™ Ethernet collateral will be reusable with the Virtex-4 MAC.

Reference designs are available that demonstrate useful techniques for optimizing your Ethernet system designs. The LocalLink LLTEMAC checksum offload peripheral, available with the Gigabit System Reference Design (XAPP536) demonstrates how to accelerate the TCP performance of your network endpoint.

Development Boards
Xilinx provides a family of development boards for immediate prototyping of your system design. These include:

• The ML403, a low-cost development platform featuring the Virtex-4 FX12 device, includes a tri-speed Ethernet PHY for Ethernet copper connectivity
• The ML405 development board provides a superset of the ML403, with additional serial connectivity options enabled by the Virtex-4 FX20 RocketIO transceivers

Conclusion
The embedded tri-mode Ethernet MAC in Virtex-4 FX devices provides unparalleled flexibility for today’s Ethernet systems designers; spanning:

• Hub, switch, and router systems topologies
• Tightly coupled network processing functionality utilizing embedded processors and custom logic
• Embedded processing shared bus subsystems
• Direct low latency connectivity to packet storage
• Cost effective interoperability with future, current, and legacy physical layer standards

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