Virtex-4 FPGAs make complete memory interface solutions possible.
Building interfaces to high-performance memory devices presents
challenges such as high-speed synchronous data capturing,
along with implementing complex physical-layer interfaces and
control logic.
Virtex-4 FPGAs solve these challenges with advanced silicon
capabilities, including ChipSync™ source-synchronous technology,
Xesium clocking, and Smart RAM.
- ChipSync technology provides 80 ps resolution for
clock-to-data alignment, ensuring reliable data capture
- 500 MHz Xesium differential global clocks minimize skew
and jitter, providing increased design margins
- 500 MHz Smart RAM blocks have built-in FIFO
functionality, minimizing design size
- Column-based I/O eliminates memory interface placement
restrictions, alleviating board congestion
To shorten design time, Xilinx provides expert guidance in the
form of free hardware-verified reference designs, application
notes, user-friendly tools, and advanced development systems.
This combination of unique silicon capabilities and comprehensive
support enables you to build and verify robust memory interfaces
quickly and easily.
The advanced memory development system, ML 461, offers
an excellent platform to develop and verify high-performance
memory interfaces.
Xilinx also offers a menu-based tool, the memory interface
generator, to further customize reference designs (Figure 2). The
tool generates the pin placement file and a complete modular set
of HDL files.
You can download the reference design, application
notes, memory interface generator, and other resources
for memory interface designs by visiting
www.xilinx.com/virtex4/. If you are interested in
purchasing the ML461, please contact your local sales
representative, or e-mail designkits@xilinx.com.
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