Xilinx® introduced FPGAs with integrated multi-gigabit serial transceivers (MGTs) more than three years ago. Since then, Virtex-II Pro™ devices have enabled hundreds of applications to move from parallel interfaces to high-speed serial interfaces, as designers took advantage of the integrated RocketIO™ transceivers.

With Virtex-II Pro devices, Xilinx led the industry with a transceiver capable of 622 Mbps-3.125 Gbps operation. Xilinx continues this trend with its new Virtex-4™ family, in which RocketIO transceivers can operate from 622 Mbps to more than 11 Gbps (Figure 1). This broad speed range – coupled with a host of user-friendly, programmable options – creates an extremely flexible multi-gigabit transceiver.

Multiple Interface Standards
One trend occurring in multiple end-market segments is the widespread adoption of hig-speed differential signaling schemes to address increased bandwidth demands. As designs move to faster interface speeds, a serial implementation saves power, board space, design complexity, and ultimately cost. Virtex-4 RocketIO transceivers were designed to enable high-speed data transmission for many different protocols. Table 1 shows all of the serial standards supported in Virtex-4 FPGAs.

Flexibility and Programmability
Xilinx brings its approach to FPGAs – making them user-programmable, with maximum flexibility – to its multigigabit transceivers. This approach has impacted both of the major functional components of the RocketIO transceiver: the physical media attachment (PMA) block and the physical coding sublayer (PCS) block.

PMA Block
The Virtex-4 RocketIO PMA block supports all major serial I/O standards and is compliant to their physical layer requirements. For example, the RocketIO transceiver meets the OC-48 SONET/SDH specification (2.488 Gbps) for both transmit jitter generation and receive jitter tolerance.

This same transceiver can also meet the requirements of the Fibre Channel physical layer specification, and it can do so at 1.0625 Gbps, 2.125 Gbps, 4.25 Gbps, and 8.5 Gbps.

Other PMA features of the Virtex-4 RocketIO transceiver include:

• Programmable transmit pre-emphasis (3-tap)
• Programmable active receive equalization
• Programmable decision-feedback equalization (DFE)
• Integrated receiver AC-coupling capacitors (user-bypassable)
• PCI Express-compliant electrical idle support
• PCI Express-compliant beaconing support
• PCI Express-compliant spread spectrum clocking support
• Multiple loopback modes, including a PMA Rx to Tx path

User-programmable clock correction sequences (CCS) allow synchronization differences between remote transceivers to be tolerated and corrected. Channel bonding sequences (CBS) enable you to connect multiple RocketIO transceivers together to create a logical channel with even more bandwidth. All of these features are compliant to industry standards (making designs easier to complete), while still supporting proprietary designs.

For applications requiring lower latency, a new feature of the Virtex-4 RocketIO transceiver is a reduced latency mode that allows you to bypass the receive and transmit FIFOs (as well as other function blocks), offering a 50% reduction in latency from previous generations of Xilinx transceivers.

Other PCS features of the Virtex-4 RocketIO transceiver include:

• Multiple loopback modes, including a PMA Rx to Tx path
• Comma detection, including A1A1A2A2 for SONET applications
• Clock correction/channel bonding receive elastic buffer
• Autonomous CRC-32 blocks (one for transmitted data and one for received data)
• Dynamic configuration bus to access every PCS attribute dynamically, including CCS and CBS
• 64B66B block sync, gearbox, encoder/decoder, and scrambler/descrambler
• 8B10B encoder/decoder
• Built-in clock dividers to reduce the need of DCMs for clocking use models Figures 2 and show block diagrams of the Virtex-4 PCS (both receiver and transmitter).

For more information about the Virtex-4 FPGA family, visit www.xilinx.com/virtex4/. For more details about the functionality and design recommendations with Virtex-4 RocketIO transceivers, see the Virtex-4 RocketIO transceiver user guide at www.xilinx.com/bvdocs/userguides/ug076.pdf.

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