We are living in very exciting times today, with new, compelling consumer applications springing up seemingly out of nowhere. These exciting times can be applied specifically to FPGAs, as we continue to see growth and widespread acceptance of the concept of programmable logic by the marketplace at large.

The wind in the sails of the FPGA industry is our old friend Moore’s Law, which states that semiconductor devices will see a doubling of available transistors every 18 to 24 months. The increase in transistor budgets available to designers and the movement to ever-tighter process geometries translates directly into devices with rising performance levels and smaller die areas.

A good example of this is the recent introduction of FPGAs produced using 90 nm process geometries. Smaller geometries have allowed FPGAs with more logic elements and embedded memory, while at the same time decreasing the die area needed for the solution. A part with a given performance level using 130 nm process geometries can now be produced with a higher performance level in a smaller die area at 90 nm. Die area and yield have a great impact on device costs, so FPGA manufacturers can offer these new 90 nm families at decreasing price points.

Why is this important, and how does it change the systems landscape? Lower price points for a given performance level allow system designers and system architects to have an end product with increased performance and a lower BOM. For systems manufacturers, this leads to increased profitability, a lower overall system cost, or both.

At face value, this situation seems rather straightforward: lower device costs equal lower system costs – everyone is a winner. However, the real answer to this question goes much deeper than lower costs. To gain a better perspective on this issue, we must explore some of the background of the FPGA market and the ASIC industry as a whole.

A Difficult Design Environment
In today’s market environment, there are a series of trends adversely influencing the ASIC design community. One of the trends most often discussed is the rise in NRE, which are costs associated with the design of ASICs. Figure 1 shows how these costs have increased by process geometry. NRE costs have risen in large part because of the rising device complexity. As the possible gate counts have increased at each process node, so too has the task of assembling these gates into a design that meets the needs of the market.

With its low-to-none NRE costs, programmable logic is a great aid to designers who need to prove out their designs in the shortest amount of time to meet a moving market window but do not have the engineering or financial resources necessary to commission a new system-on-chip design. Figure 2 shows the relationship between design cycle times, gate count, and product life cycles. Designers are under pressure to hit a market window that is shrinking, while at the same time their designs are becoming more complex. These trends are at odds with product life cycles, which are also shrinking.

The net effect of these trends is to make the design environment more challenging for ASIC designers. Even before a design is complete, the market at which it is aimed could have changed – necessitating changes in the design itself. This quickly becomes a no-win situation for all concerned.

Furthermore, as the cost to create a complex ASIC solution increases, so too must the size of the market towards which the solution is targeted. If the design costs for a complex ASIC are in the $30 million range, the size of its target market must be many times larger than the design costs just to recover the initial investment in the silicon. Admittedly, there are not many applications today that can command such high unit volumes to guarantee the recovery of this initial investment.

An additional detrimental effect is the decline in ASIC design starts because of rising design costs, decreasing product life cycles, and shrinking market windows. Several of these trends and ASIC design start numbers for various ASIC product types (including FPGAs and PLDs by end application) are detailed in an upcoming report from Semico titled, “ASIC Design Starts: An Industry in Transition.”

Low-Cost FPGAs Change the Equation
Now that we’ve reviewed current trends in the ASIC market, we can now look at how low-cost FPGAs can change the landscape to one more favorable for designers. Designers can now apply the traditional strengths of programmable logic to their system solutions – namely the low cost of entry, off-the-shelf availability, short design cycles, reprogrammability itself, and a known and working architecture. Plus, they can use FPGAs as test vehicles to examine and prove out different types of semiconductor intellectual property (SIP) with an ease that is impossible in standard cell or SoC markets. ASIC designers can test out several different types of SIP using FPGAs in the same time it took just to try out one type of SIP using the traditional standard cell or SoC route. This in itself is a great aid to ASIC designers in arriving at the best possible silicon solution.

However, the road for FPGAs does not end here; this is merely the start of the story in terms of aiding ASIC designers. Previously, when FPGA silicon was more costly, ASIC designers could successfully prototype with FPGAs and enter into limited production with their FPGA solution. But at some point, usually between 30,000 and 100,000 units (depending on the price sensitivity of the end application), the design would change over to a full-blown ASIC solution. At this point, many of the gains seen through the use of programmable logic were given up; designers were back on a more traditional ASIC path, with all the previously mentioned problems and pitfalls.

As shown in Figure 3, lowcost FPGAs have pushed out the point at which a standard cell or SoC solution must be employed to arrive at the absolute lowest cost. This chart also takes into consideration the total cost to create the ASIC solution (NRE charges and mask set costs, for example), as compared to the same cost to create the silicon solution using programmable logic. The benefits are numerous, particularly the ability to use a silicon solution that fits into market windows and is at the right price point.

Conclusion
As FPGA vendors continue to use smaller process geometries when they become available, the ASIC industry will see a further extension of FPGAs into applications where they can deliver a solid solution at the necessary price points.

Designs and end-system solutions that might not have made it into production because of a prohibitively long design cycle now have a much better chance of succeeding, whereas before they might have been cancelled because they couldn’t make that ever-important market window.

The introduction of lowcost, full-featured FPGAs has changed the systems landscape for the better. Today, ASIC designers or system architects can use a programmable logic solution with the knowledge that a FPGA can be used farther into the production cycle than was previously possible.

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