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Since joining the CPLD market in 1992,
Xilinx® has gone from being the new kid on
the block to the third largest CPLD supplier,
and is close to grabbing the number-two
position in both volume and sales dollars.
Growth has come from listening to customer
input and creating innovative ideas
to satisfy customer needs.
Continued improvement is an ongoing
goal. Toward this end, Xilinx has extended
the features of its 32- and 64-macrocell
CPLD devices by augmenting a feature, currently
only available on higher density parts,
that will help ease design difficulties and
reduce total system costs. In conjunction
with added features, Xilinx is also offering
new packages to decrease the cost-per-I/O
for small footprint packages. These new
packages will help Xilinx continue to penetrate
low-cost, battery-operated devices.
Xilinx is achieving CPLD market share
growth through both traditional applications
such as computing, data processing,
networking, and telecommunications, and
non-traditional applications such as consumer
products (set top boxes and large
screen TVs – both plasma and LCD) and
key handheld markets (PDAs, handset, and
other battery operated products). With
new market success and continued traditional
market use, CPLDs will continue to
show growth in system logic solutions.
New Banking for CoolRunner-II CPLDs
Xilinx has re-introduced its CoolRunner-II™
32- and 64-macrocell devices with an
added feature known as I/O banking. I/O
banking is useful in systems that use different
supply voltage levels on the same
printed circuit board. Usually, a mismatch
of voltage levels occurs between a system
processor and the devices with which it
communicates. This communication may
be as simple as a serial to parallel conversion,
or as integral as a processor interface
to a display.
Another example is the connection of a
processor to an external memory card such
as CF (compact flash) or SD (secure digital).
Because of competition and constant
price pressures, high-profile devices such
as processors must continue to use
advanced process technologies. These
process technologies continue to lower
voltage swings because of the physical
properties of wafer geometries.
Yet standards organizations in markets
like memory cards, wireless communications,
and bus architectures go through
specification changes more slowly. To bridge
the gap, voltage and I/O translation is a necessary
component in today’s architectures.
Care must be taken to match input and output
voltage-switching thresholds for that
particular voltage standard.
Designers face the challenge of pasting
together many logic level standards on a
variety of part types. What device can do
the job and yet leave room for design
upgrades or changes? Discrete devices can
usually address this mismatch, but may add
cost, power consumption, printed circuit
board layers, and area to a design. They
may have limited functionality – and you
may have to buy additional parts to completely
solve the problem. The more parts
you use, the higher the chance of picking a
part that may be discontinued, and the
more purchase orders and stocking requirements
you generate. Plus, if you need to
assemble more parts, the board assembly
cost will probably increase. But if a simple
AND gate is all you need, a discrete logic
device is probably the right choice.
Let’s look at the case where you need
more than just a simple gate. CPLDs have been continually cost reduced and are
now on par with some discrete logic
devices. If you are using multiple discrete
logic devices, the benefits of a CPLD
become even more appealing.
This trend opens up a whole new level
of integration at a low price point. For
the first time in history, CPLDs can compete
with discrete solutions, add functionality,
and cost less. For instance, a
typical voltage translation device usually
costs from $0.50 to $3.50, depending on
volume, package type, the number of
I/Os to be used, and the process technology
of the device. CPLD devices are
below $1.00 for the smallest density and
lowest cost package. But you get a whole
lot more within that single CPLD than
any discrete function logic device.
With the addition of I/O banks on
CoolRunner-II 32- and 64-macrocell
CPLDs, voltage and standard I/O translation
can occur in very small, cost-competitive
CPLDs. When using a
CoolRunner-II CPLD, other benefits also
include the following:
- Security
- Input hysteresis
- Optional output control
- Low power operation
- Multiple package options
with varying I/O
- IEEE1149.1 Boundary Scan test
- Adjustable from 1.5V to 3.3V
With these features, CPLDs offer more
than voltage translation – and can do a lot
more. Because discrete level shifters perform
a specific task, you may be stuck with
a specific I/O choice. With Xilinx CPLDs,
you get choices on I/O, and you can use
them for other functions. Thus, they are a
better choice when you need level translation
versatility and some logic, extra I/Os,
or other system integration functions. See
Table 1 for features and package types.
Table 1 – CoolRunner-II family overview
|
CoolRunner-II Family of CPLDs |
|
Features | XC2C32A | XC2C64A | XC2C128 | XC2C256 | XC2C384 | XC2C512 |
| Macrocells | 32 | 64 | 128 | 256 | 384 | 512 |
| FToggle(MHz) | 450 | 333 | 416 | 416 | 416 | 416 |
| FSYSTEM(MHz) | 303 | 238 | 263 | 238 | 217 | 217 |
| Max I/O | 33 | 64 | 100 | 184 | 240 | 270 |
| I/O Banks | 2 | 2 | 2 | 2 | 4 | 4 |
| LVCMOS, LVTTL (1.5, 1.8, 2.5, 3.3) | Yes | Yes | Yes | Yes | Yes | Yes |
| HSTL, SSTL | No | No | Yes | Yes | Yes | Yes |
| DualEDGE | Yes | Yes | Yes | Yes | Yes | Yes |
| DataGATE, CoolCLOCK | No | No | Yes | Yes | Yes | Yes |
| Standby Power (µW) | 28.8 | 30.6 | 34.2 | 37.8 | 41.4 | 45.0 |
| Advanced Security | Yes | Yes | Yes | Yes | Yes | Yes |
| Packages (Size, Type) | Maximum User I/O |
| VQ44 (10 x 10 mm, leaded) | 33 | 33 | - | - | - | - |
| PC44 (16.5 x 16.5 mm, leaded) | 33 | 33 | - | - | - | - |
| CP56 (6 x 6 mm, chip-scale) | 33 | 45 | - | - | - | - |
| QFG32 (5 x 5 mm, Pb-free) | 21 | - | - | - | - | - |
| QFG48 (7 x 7 mm, Pb-free) | - | 37 | - | - | - | - |
| VQ100 (14 x 14 mm, leaded) | - | 64 | 80 | 80 | - | - |
| CP132 (8 x 8 mm, chip-scale) | - | - | 100 | 106 | - | - |
| TQ144 (20 x 20 mm, leaded) | - | - | 100 | 118 | 118 | - |
| PQ208 (28 x 28 mm, leaded) | - | - | - | 173 | 173 | 173 |
| FT256 (17 x 17 mm, BGA) | - | - | - | 184 | 212 | 212 |
Additional Low-Cost Packages
With the migration of CPLDs into nontraditional
markets, package form factor
and cost have become growing concerns.
The Xilinx CPLD group has listened to
customer needs and found a better small
form-factor package. This package is a low-cost
alternative to more expensive chipscale
BGA packages with similar I/O
counts. The MLF (micro lead frame) package,
shown in Figure 1, is small and packs
a lot of I/O.
Xilinx has introduced two new MLF
packages for the CoolRunner-II family of
CPLDs: a 32-pin QFG (quad flat no lead,
Pb-free) package with 21 I/O for the 32-macrocell device, and a 48-pin QFG package
with 37 I/O for the 64-macrocell
device. These additions bridge the gap
between more expensive chip-scale BGA
and low-cost thin quad flat pack packages.
MLF packages, also known as QFN
(quad flat no lead), offer small sizes and
high I/O counts, but unlike their BGA
chip-scale cousins, are easy to assemble and
easy to probe. For assembly, they are like
regular 0.5 mm pin spacing thin quad flat
pack (TQFP) packages. This makes pin
alignment and solder reflow very easy compared
to BGA packages.
For debug, MLF packages have external
pins that can be probed just as easily as a thin
quad flat pack package. These features make
it a great addition to the CoolRunner-II
family of CPLDs for consumer products.
These MLF packages also offer better
electrical characteristics. With their small
size, bulk capacitance and inductance are
lower than TQFP packages.
Conclusion
Many product choices are available when
considering voltage translation, but
CPLDs are the best choice for many reasons.
You get additional logic capability,
more package choices, lower power, free
JTAG testability, I/O options, advanced
security, and cost savings. Current users
will benefit from the same pin-out, as well
as the new I/O banking feature.
Novice users can find out how to use
these new CPLDs at www.xilinx.com/cpld/.
Don’t forget that the design software is
always free and easy to use. Download your
copy of ISE™ WebPACK™ software at
www.xilinx.com/products/design_resources/design_tool/index.htm to start your design
today. With these design tools and worldclass
support, Xilinx CPLDs make a great
choice for logic solutions and replacement
of discrete logic devices.
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