Market leadership in the fast-moving electronics market continuously demands more innovative and cost-effective products. With an ever-shrinking time-to-market window, design tools and prefabricates are important elements of success.

But the right development platform can make all the difference between success and failure, harmonizing the contradictory requirements of being standard and highly configurable at the same time.

Combining Xilinx® FPGAs with the Xylon logicBRICKS IP cores library, Xylon’s feature-rich Multimedia FPGA Platform is ideal for addressing the time-tomarket and flexibility needs of the highvolume customer base. You can quickly turn system designs running on this generic FPGA development platform into specialized products. Such a design approach retains a large portion of design reuse through different hardware (IP cores) and software modules. You can reuse these same modules in many system designs for different applications.

Multimedia FPGA Platform
The basic functional blocks of the Multimedia FPGA Platform are output to displays, with inputs provided from video, human machine interface, and communication interfaces. These functional blocks support a variety of different displays, video input types, input devices, or communication interfaces.

The Multimedia FPGA Platform is an FPGA design based on hardware modules in the form of IP cores. You can add additional features using third-party IP cores or by designing a customer-specific circuit.

The main components of the Multimedia FPGA Platform are:

• logiCVC – a compact video controller for display driving
• logiBITBLK – for 2D graphics acceleration
• logiCAN/logiUART – for communication
• UltiWIN – for frame grabbing (video input)
• UltiMEM – a multi-port SDRAM/ DDRAM memory controller

In addition, the DCMs provide finer clock generation and eliminate the need for costly clock-generation ASSPs, while digital termination and DDR support enable better and lower cost support for SDRAM or DDRAM memories.

Figure 1 shows the Multimedia FPGA Platform block schematic configured for an automotive backseat entertainment application. This example is significant because it has the capability to show a live video stream on any display screen. We accomplished this by instantiating more than one logiCVC for multiple display driving and instantiating more than one UltiWIN for simultaneous video input streaming.

A DVD, VCR, or camera CVBS output is used as the first video source, while a MOST network is used as the second. The CVBS analog signal is converted to an ITU656 digital signal by a composite video signal decoder, an ASSP component. The MOST MAC and MPEG decoder are customer-added IP cores. The I2C and GPIO IP cores are used for the keyboard and touch controller interface. The UltiMEM IP core is configured for unified memory architecture and six access ports. The 32-bit DDRAM assures 800 MBps bandwidth for display refresh, video streaming, graphics acceleration, and CPU program execution. The logiCAN and logiUART-local interconnect network (LIN) IP cores are used for network connections with in-car body electronics.

Memory Bandwidth Requirements
The selection of memory bandwidth is important for system performance. The six IP cores share common memory, as shown in Figure 1. Two logiCVC driving displays of 400 x 234 resolution and 16 bpp color depth require 16 MBps each. Two UltiWIN processing CVBS video sources require 54 MBps each. The Xilinx MicroBlaze™ soft-processor core running at 100 MHz requires 400 MBps, while the logiBITBLK, processing 16 bpp images and running at 50 MHz, requires 100 MBps. This gives a total bandwidth requirement of:

2 x 16 MBps + 2 x 54 MBps + 400 MBps + 100 MBps = 640 MBps

System Gate Count
Table 1 shows the size of each IP core and the total number of slices required for the backseat entertainment FPGA design. Every single IP is compact with a low gate count, resulting in a lower cost solution.

The complete backseat entertainment system is a complex multimedia application that fits into a Spartan-3 XC3S1000 device, leaving approximately 2,000 slices for extra FPGA circuits. A separate display controller application driving a single display, including 2D graphics acceleration and a UMA memory architecture, fits into a smaller Spartan-3 XC3S200 device.

We reduced costs further by using the MicroBlaze core, which eliminates the need for a separate external CPU. The IP core integation and system configuration for the MicroBlaze core is provided by the Xilinx Embedded Development Kit (EDK).

End Applications
The Multimedia FPGA Platform is primarily aimed at the automotive market, including applications such as navigation, infotainment, backseat entertainment, and driving assistance.

Example infotainment applications include such automotive displays as VCR videos, game consoles, rear-parking cameras, and navigation systems. Figure 2 shows a backseat entertainment prototype system displaying a contemporary game console on one display and a DVD movie on another display.

Driving assistance is an another example of an automotive application using multimedia platform IPs. The system comprises synchronized stereo video camera inputs, a DSP algorithm for image processing, and CAN IP for communication with dashboard or other human interfaces.

Xylon is in the process of designing an automotive reference board, which provides the ability to prototype or evaluate the Multimedia FPGA Platform by connecting displays, input devices, vehicle communication buses, and video signal sources. Other multimedia applications are equally suitable, such as consumer, medical, and measurement instrumentation or factory automation.

Today, automotive OEM and first-tier manufacturers have used Xilinx FPGAs and Xylon IPs to develop infotainment systems.

Conclusion
The value of the Multimedia FPGA Platform from Xylon is in the high number of different displays tested; the broad feature set; and the ability to configure for performance, price, low development, and production cost, all with virtually no obsolescence.

Xilinx FPGAs, and in particular the Spartan-3 family with its low cost-per-gate and rich architecture, provided an excellent base on which to build. Combining Spartan-3 devices with Xylon logicBRICKS IP cores provided the ideal combination of feature set, form factor, performance, and time-to-market capabilities for the development of the Multimedia FPGA Platform.

For more information about the Multimedia FPGA Platform and logicBRICKS Xylon IP library, please contact us at sales@logicbricks.com, or visit www.logicbricks.com.

Multimedia FPGA Platform Features Displays supported: wide-resolution range 128 x 64 to 1280 x 1024 pixels; wide range of color depths 1- to 24-bit bpp, TFT/STN and other flat panel displays; 8- to 32-bit memory interface, overlays, multiple display support Acceleration: ROP2 operation, block fill, transparency, color expansion, pattern operations Memory interface: flexible multiport memory controller, unified memory architectures for costsensitive applications, priority, round-robin and mixed-port arbitration policy, configurable data width for access port and configurable memory bus Video input: YUV-RGB and deinterlace, picture position, picture cropping, picture scaling using multi-pass bi-linear interpolation, multiple video input source support Communication: CAN controller and UART improved for LIN bus

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