If you are pushing the limits of performance and density in an FPGA, then you are also likely facing problems that threaten your design deadlines. Long place and route runtimes and repeatability of results are two common sources of anxiety.

Also, traditional FPGA tools provide a flat, push-button implementation approach – a flow that provides few clues about how to improve your design goals and even fewer opportunities to make the necessary changes.

If you can relate to these challenges, Xilinx® offers a new tool that will put you in control of your design. The PlanAhead™ hierarchical design and analysis tool allows you to employ ASIC design methodologies for complex FPGAs. PlanAhead software easily integrates into your existing flow between synthesis and place and route, as shown in Figure 1. You can analyze, detect, and correct many potential problems before place and route. And with its block-based incremental capabilities, you can divide and conquer your design one block at a time.

Analysis
PlanAhead design tools take a synthesized EDIF netlist as input and one or more UCF files for constraints. The powerful and easy-to-use graphical environment displays the Xilinx device that you have targeted (see Figure 2). At this point you have several tools available to explore your design space.

Timing Analysis
TimeAhead is a flexible timing analyzer built into PlanAhead software. It allows you to estimate route delays before running place and route. Using the PlanAhead block-based approach, the accuracy of timing estimates will improve as blocks in the design are implemented through place and route.

Statistics
You can generate a detailed statistical report for any block in your design that includes information on clocks, resource utilization, RPMs, carry chains, clock regions, and the number of internal versus external nets. This could help you narrow down problems in your design to specific blocks or modules that you could then re-code or re-synthesize with different options.

Schematic Viewer
A comprehensive schematic viewer can help you navigate timing paths, trace through cones of logic, or determine the floorplanned block connectivity. Some simple net and pin tracing capabilities within the schematic viewer can save you hours wading through VHDL/Verilog files.

Connectivity Display
PlanAhead software bundles all nets connecting any two floorplanned blocks into a single line, with thickness and color reflecting the number of such nets. This bundled connectivity shows the flow of data through the design and is extremely useful in arriving at the “right” floorplan.

Constraints Editing
You can view, edit, add, and delete any of your constraints and see the effect of timing constraint changes by re-running TimeAhead. This eliminates the need to rerun place and route – a lengthy process – just to verify constraint changes. If you decide that certain paths are not important, you can false path them, decide that certain clocks need to be tightened, or add a MAX_DELAY constraint on a long meandering net.

Design Rule Checks (DRCs)
PlanAhead software sports a comprehensive set of design-rule checks to flag potential problems before launching a time-consuming place and route run:

• SSO limit violations
• I/O bank rule violations
• Clock region rules
• Carry chain height
• DSP48 internal register optimization

Device Selection
It is easy to explore different devices (within compatible families) for a netlist because PlanAhead tools can open multiple device views (floorplans) on the same netlist. In combination with TimeAhead, this enables you to decide on the speed grade that matches your target performance and the optimal size of your Xilinx part. It can also help you choose your pin package.

Multiple Floorplans
PlanAhead software has the ability to open multiple device views on the same netlist and create a different floorplan in each of the device views. You can analyze each floorplan for utilization and performance characteristics and ultimately run through place and route. This gives you a powerful what-if mechanism for design space exploration.

You can import the placement of your block or entire design and make changes to the placement locations. PlanAhead design tools give you very easy-to-use cross-probing functionality between the netlist tree display, schematic, placement, timing paths, and user floorplanned blocks. Figure 3 shows the post-place and route environment. The PlanAhead analysis features work together to make it easy for you to comprehend the effect of physical implementation on performance.

Metric Maps
With metric maps (introduced in the latest PlanAhead release), you can detect problem areas such as a cluster of negative slack instances within a certain hierarchical module on the placement surface. Congested areas or utilization issues are also detectable. Better, faster, and smarter visualization puts you firmly in control of the FPGA and leads to faster turnaround times in fixing problems.

Block-Based Design
If you’ve ever struggled to get a giant FPGA out the door on time, you might have wondered how to break up your design into smaller, more manageable blocks. Imagine a flow that lets you focus your optimization efforts on a critical block, implement it, and verify its performance before tackling the rest of the design. You may have also wished for a flow that enables you to divide up a design between team members.

PlanAhead software was built from scratch to be your hierarchical design tool. At its core lies the PBlock (or Physical Block): a physical design entity that contains one or more logical (RTL or structural EDIF) hierarchical instances.

Simply create a PBlock, assign a region for it, export its netlist and relevant constraints for place and route, import its placement results, and verify its timing. PBlock technology enables several key methodologies.

Flexible Block Partitioning
PBlocks can comprise any number of hierarchical instances or logic elements (LUTs, FFs). PBlocks need not adhere to your original logical hierarchy and can be dynamically redefined whenever necessary throughout your flow. Let’s explore the advantages of this technology.

Performance-Based Floorplanning
PBlocks can group logic together to improve performance on your design. Corralling critical paths into smaller regions on the device can potentially improve performance through reduced route delays. You can use any of PlanAhead’s analysis features to drive PBlock creation and floorplan generation. Once defined, a floorplan can absorb minor to moderate changes to the netlist to help keep your place and route results predictable.

Block Analysis
If design analysis reveals that your critical paths are contained by a few hierarchical instances, you might consider the following technique. Create a PBlock with these instances and export the PBlock to place and route. PlanAhead software will also export timing constraints relevant to those instances.

Your place and route results serve as a timing sanity check – if the trial PBlock does not meet timing, you are guaranteed that the logic will not meet timing in the global context. It is easy to pinpoint and address the potential showstoppers in your design.

Bottom-Up Flow
Once a PBlock has run through place and route and its results look promising, you can use the placement results for the PBlock in a powerful team-based design flow. For example, the design manager could divide up the logic into PBlocks and assign one or more to each team member (Figure 4). Team members focus on achieving satisfactory results for each of their assigned PBlocks and return those results to the manager.

The manager then stitches the design back together by importing each PBlock result into PlanAhead software as it arrives. Because PlanAhead design tools do not lock down routing, the design manager will need to launch a final route run to complete the design.

IP Re-Use
PlanAhead software has the ability to export any IP module, which can then be run through place and route. Once you are satisfied with performance, you can save the module’s placement in your team’s IP library. Another team member can import the IP and its placement into an entirely new design.

PlanAhead design tools also allow IPs to be moved around on the device – the relative placement of all logic elements within the IP is maintained and the net route delays should see minimal variation. The time spent to meet performance on your IP modules need not be repeated for each design using this IP.

Incremental Design
Xilinx ISE™ software’s incremental guided implementation flow in place and route requires you to floorplan your design. This guiding flow will re-use your previous implementation results in conjunction with the floorplan to help preserve results in the new implementation. You can use PlanAhead software to easily generate the necessary floorplan for guided incremental flow.

With larger FPGA design sizes, more users are complaining about unpredictability of results and long place and route runtimes. PlanAhead block-based flows put you in control of your larger designs and their increasing complexities.

Table 1 offers several examples of customers who have had marked results after adopting the PlanAhead methodology.

Table 1 – Customer designs demonstrate a boost in performance and productivity with PlanAhead software.

Conclusion
Even though FPGAs continue to grow in size and sophistication, performance requirements and time-to-market pressures remain status quo for FPGA designers. Existing design flows and methodologies are struggling to keep pace, but PlanAhead software provides a revolutionary boost to your current flow.

Intuitive and powerful, its design analysis and block-based hierarchical design capabilities put you in control. To learn more about PlanAhead design tools, visit www.xilinx.com/planahead/.

Printable PDF version of this article with graphics.  (4/18/05) 400 KB

	Device	Before	After
Customer A	XC2V1000	Inconsistent Results: 25 MHz to 60 MHz	Consistently Exceeding 63 MHz
Customer B	XC2V8000	9 Hours Place and Route Runtime: 147 MHz	3 Hours Place and Route Runtime: 172 MHz
Customer C	XC2VP70	54 MHz	102 MHz
Customer D	XC2V6000	Design Time 3 Weeks: 160 MHz	Design Time 3 Days: 178 MHz
Customer E	XC2V4000	120 MHz	170 MHz
Customer F	XC2V4-LX60	93 MHz	109 MHz