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Device power consumption has become one
of the leading design issues facing FPGA and
CPLD engineers today. Device consumption
can affect everything from cost and longevity
of the device in your project to system performance
and battery life in hand-held
applications. Xilinx® design tools have
expanded over the last few releases to offer
you more ways to generate accurate estimates
of your device power consumption.
The Power Essentials
There are two main components to FPGA
chip power consumption:
- Dynamic power is largely determined
by the switching power of the core and
the switching speed of the I/O.
Dynamic power is largely affected by
capacitive load, supply voltage, and
switching frequency.
- Quiescent power is dominated largely
by transistor leakage current and by
DC current from a few specialized
FPGA circuits.
The drive to lower FPGA costs drives
transistor size down, which tends to raise
quiescent power consumption. Design
demands also continue to force design performance
faster, leading to higher switching
rates and higher dynamic power
consumption.
Xilinx Virtex™-4 FPGAs can deliver as
much as 70% more performance than the
nearest competing FPGA offering.
Normally, this trend might raise dynamic
power consumption. Designs are also getting
denser year to year; again, in normal
circumstances this tends to raise static and
dynamic power. However, the Virtex-4
family offers dramatic static and dynamic
power reduction through architecture,
design, and process, offering as much as
1/10th the static power of other 90 nm
FPGAs. You can also obtain a 20X power
reduction using the available Virtex-4
embedded functions.
How has Xilinx been able to reduce
power in its Virtex-4 FPGA? Triple-oxide is
the Virtex-4 process innovation that has
reduced leakage current, whereas two-oxide
thickness was used for Virtex-II Pro devices
and all past families. However, Virtex-4
FPGAs add a third middle-thickness-oxide
transistor, thereby reducing static power.
The Virtex-4 architecture has also
enabled dynamic power-per-CLB to be
reduced by 50% at comparable frequencies.
Even at a 50% higher operating frequency,
Virtex-4 devices reduce dynamic
power by 20%.
An overall increase in power demand also
emphasizes average junction temperature
and thermal power consumption. Exceeding
the allowable junction temperature leads to
reduced system performance, forces reduced
device utilization, and reduces device reliability.
The more information you have about
junction temperature and how your design
will affect it, the more informed your decision
will be on package types and thermal
design considerations, as well as where you
can make design changes to help reduce
potential thermal problems.
Power consumption is design-dependent
and affected by output loading, system
performance (switching frequency),
design density (number of interconnects),
design activity (the percentage of interconnects
switching), logic block and
interconnect structure, and power supply
voltage levels. You can perform power calculations
at three distinct phases of the
design cycle:
- Concept phase – calculating a rough
estimate of power based on estimates
of logic capacity and frequency of
operation. Supported using Xilinx Web
Power Tools.
- Detailed design phase – calculating
power more accurately based on
detailed information about how the
design is implemented in the FPGA.
Supported through XPower and included
with all copies of ISE™ software.
- System integration phase – measuring
power using benchtop instrumentation
(board-level measurements).
Xilinx Power Tools utilize “activity
rate” to reach accurate power estimates.
Clocks and other input signals have an
absolute frequency. Synchronous logic
signals use a percentage
“activity rate” relative to
the associated clock. An
activity rate of 100%
indicates that a net is
expected to change state
on every clock cycle.
Activity rates can be set
globally (12% of the nets
switch each clock cycle),
on groups of signals, or
individual signals.
“Activity rate” allows you
to adjust clock frequency
in XPower and see the
effect on power consumption to your
design results. The frequency of logic elements
displayed by XPower is a function
of their output signal(s).
Power Tools
The Xilinx Power Central website for
FPGA and CPLD power analysis
(www.xilinx.com/power/) contains links to
Xilinx web-based power tools, information
on XPower, ISE-integrated power analysis
software, white papers, design examples,
and links to power-centric partner products
and software.
Web-Based Power Tools
Web-based power estimation is the quickest
and easiest way to get an idea of device
power consumption early in the design
flow. Xilinx offers a complete set of webbased
power tools on Power Central. A new
version is released every quarter, so information
is current, and no installation or
downloading is required – just an Internet
connection and a web browser. You can
specify design parameters and save and load
design settings, eliminating the need to reenter
design parameters with iterative use.
Just an estimate of design behavior and a
target device will get you started.
Version 4.1 of Xilinx web-based Power
Tools was released in March 2005. This
new release is designed to help customers
quickly and easily estimate the power
consumption of their target Xilinx device,
and in particular includes important new
Virtex-4 LX, SX, and FX family enhancements
(Figure 1).
- Power results are now affected by
changes in ambient temperature – one
of the only power tools able to consider
ambient temperature
- Iccintq and Iccauxq have been updated
with new, more accurate figures
- The Virtex-4 XtremeDSP™ block
power has been updated with new
measurements at low, medium, and
high toggle rates
- Latest thermal data updates for all supported
devices
In addition, new updates that affect both
Virtex-4 FPGAs and other Xilinx device
families include:
- VccInt can now be varied for Virtex-4,
Virtex-II, Virtex-II Pro, and Spartan-3
devices
- More accurate power estimation for all
open-drain outputs
- New and improved online help updated
with all features available for
Virtex-4 FPGAs and other families; all
web spreadsheets now have clickable
header links that take you directly to
online help
XPower, a free part of all Xilinx ISE design
tool configurations, allows you to get a
much more detailed estimate of your
design-based power requirements. XPower
estimates device power based on a mapped
or placed and routed design. XPower calculates
an estimate of power with an average
design suite error of less than 10% for
mature in-production FPGA and CPLDs. It
considers device data along with your design
files and reports estimated device power
consumption at a high level of accuracy, customized
to your specific design information.
XPower is integrated directly into ISE
software and gives hierarchical and detailed
net power displays, detailed summary
reports, and a power wizard that makes it easy
for new users to run XPower. XPower can
accept simulated design activity data and
runs in both GUI and batch mode (Figure 2).
XPower considers each net and logic element
in the design. The ISE design files
provide exact resource use;
XPower cross-references
routing information with
characterized capacitance
data. Physical resources are
then characterized for
capacitance. Design characterization
is continuous and
ongoing for newer devices
to provide the most accurate
results. XPower uses net
toggle rates as well as output
loading. XPower then computes
power and junction
temperature, and can display individual net
power data as well.
Available to CPLD and FPGA users, the
XPower design wizard allows for easy data
entry to XPower and is an ideal tool for
beginners. The wizard helps you enter all
the data required by XPower to get a good
power estimate, including design files, simulation
data, operating environment, output
loading, and activity rates. The wizard
makes XPower results more accurate the
first time, and eliminates costly and timeconsuming
learning curves (Figure 3).
Power Central also contains reference
information to help you understand and
reduce power across your entire PLD project.
Application notes and user guides
with specific device and design examples
go through everything from power distribution
considerations to minimizing
power in hand-held CPLD applications.
There is also key information from power
supply partners like Intersil and Texas
Instruments on third-party power-based
products and offerings.
Conclusion
The Xilinx Power Central website delivers
everything you need to analyze your
FPGA or CPLD-based design, with tools
like XPower in ISE software, Web Power
Tools supporting the leading Xilinx FPGA
and CPLD product families, and complete
partner and reference data.
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