Xilinx® introduced the CoolRunner™-II family of CPLDs in 2001, continuing to lower power consumption through process technology improvements. This is what you would expect from a technology-driven company. But differences in this family exist that have never been employed in a reprogrammable logic device. These features deliver even lower power, higher speed, and most importantly, integrated functions that reduce system cost.

The CoolRunner-II design team looked at methods to add functionality while preserving the low-cost aspect of the current CPLD market. To this end, clock doublers, clock dividers, input hysteresis, and I/O banking were designed in from a cost-perfeature standpoint. This led to extremely creative ways to design features in the smallest amount of silicon. If the feature did not reduce system cost enough to merit the die size increase, that feature was not designed into the device. With this balance of features and cost, CoolRunner-II CPLDs offer a unique advantage when compared to other devices.

Cost-Reducing Features
Above and beyond the normal process technology shrinks that every silicon component goes through, CoolRunner-II CPLDs have very special features that help most designers lower the total components in their design. These component reductions can be very simple or very complex, depending on how creative you are as a designer. They range from clocking features to integration of simple logic functions to voltage and I/O-level differences. The principal idea behind these features is to integrate functions and simplify the designer’s task. The first and most basic is clock generation.

For most designs, a single clock source may not generate all of the necessary frequencies needed in the design. Also, if the PCB is larger than a hand-held device, clock skew may come into play. The design team considered some of these clocking design problems and created solutions internal to the CPLD.

Clock Doubler and Divider
Two features included with CoolRunner-II devices are DualEDGE and (in 128-macrocell and higher devices) a clock divider. DualEDGE flip-flops offer a performance boost for sequential operations, while the clock divider can reduce power consumption.

But that’s just the tip of the iceberg. Let’s start with a simple clock-doubling scheme where we can generate a frequency double that of the incoming clock. This yields two clock sources from a single clock input. So if you happen to need a faster clock to improve a serial data flow, DualEDGE flip-flops are a perfect fit. It also works well for improved pulse width modulation or higher resolution of timers/counters. Thus, you need not use another clock source for portions of your design that need to run faster.

Another key point is the fact that you can preserve a clock input pin. So with DualEDGE flip-flops, you get a free clock without using an input pin on the CPLD. Figure 1 shows a simple diagram of what DualEDGE flip-flops look like.

The clock divider feature (Figure 1) is another way to eliminate extra clock sources while again preserving valuable I/O pins. The neat thing about the CoolRunner-II clock divider circuit is that it actually improves duty cycle. For instance, if you have a 60/40 duty cycle on an incoming clock source, the internal divider circuitry actually performs dutycycle correction. So internal to the CPLD, this will have a 50/50 duty cycle. This may help circumvent clock skew problems and again eliminate multiple oscillator inputs.

The clock divider is not simply a divide by two; it has eight different divide-by settings (see Figure 2). So if you use the clock divider in conjunction with DualEDGE flip-flops, you can generate multiple combinations of clock frequencies. And for those troublesome odd clock frequency problems, just use an integer divide-by that yields an odd number (for example, 6, 10, 14) to get even more clock choices.

Input Pin Features
Because of the low power nature of CoolRunner-II CPLDs, the design team believed that there may be portable applications that go into noisy environments. This led to the idea of integrating hysteresis on input pins. This single feature, available on all CoolRunner-II CPLDs, adds little to silicon area but brings many advantages. With input hysteresis, the problem of noisy environments was eliminated – and as a side benefit reduced power. This power reduction is subtle, but nonetheless an advantage that other CPLDs do not include.

So how does it reduce cost? Because the hysteresis is programmable on a pin-by-pin basis, it eliminates the need for external Schmitt trigger devices. Although these components may be cheap, the extra insertion cost could prove expensive if added after the initial board fabrication. Better to be safe than sorry when it comes to reliability.

One other cost that is commonly overlooked is PCB routing and the associated costs with extra layers of circuit board material. Fewer layers is always less expensive.

I/O Banking – Voltage and I/O Standard Translation
With today’s vast selection of components, the chances of picking parts that all have the same voltage input levels are slim. Consider the time-to-market demand on today’s design engineers. If you cannot reuse some portion of the previous design, chances of making the current product release cycle are reduced. For example, a design that uses legacy ASSP devices may not line up with the same voltage or I/O structure of the new processor you just specified.

With the simple addition of a CPLD, the voltage problem goes away – and you get extra logic for all of those new features that marketing dreamed up for the next generation of products. But that’s not all, because you still need to consider if the I/O standards match. CoolRunner-II CPLDs do that for you as well.

What does this have to do with cost savings? If we look at the cost of discrete devices versus low-cost Xilinx CPLDs, you can achieve the same function for less money and get a whole lot more. Xilinx has a free downloadable tool called Logic Consolidator to show you just how much you can save (recently updated with even more parts to compare). You can download it at www.xilinx.com/products/cpldsolutions/logic_tool.htm. There are even associated documents to explain how we did the comparison.

That’s still not all, because there is more to cost than the silicon. In fact, if you look at the cost of discrete devices and the associated stocking, shipping, assembly, and routing costs, in most cases a single integrated chip costs less. Also note the CoolRunner-II CPLD’s added reliability, versatility, and low power.

Other Cost-Reducing Ideas
Still other features on CoolRunner-II CPLDs may be overlooked. OTF (on-the-fly) reprogramming is one of those features that can make your CPLD design do double duty for no extra cost. Here’s one good example of using OTF: on board power-up, use a CPLD to configure the Xilinx FPGA devices on board. Once that is complete, reprogram the CPLD to perform some system function that requires power management, integrating discrete logic functions, or implementing fixes to standard products. For more information regarding OTF, see www.xilinx.com/bvdocs/appnotes/xapp388.pdf.

If you’re designing a small-form-factor device, consider using a new package option for Xilinx CoolRunner-IIA CPLDs. The package is commonly referred to as micro lead frame or quad flat no-lead and is extremely small, yet priced similarly to standard thin-quad flat package devices. This package is an attractive way to use minimal board space and still get the great low-power operation of CoolRunner-II CPLDs.

Conclusion
Perhaps you will be able to apply some of these cost-saving ideas to your next design. If you need more information on any of these topics, there is a wealth of information from the Xilinx CPLD website at www.xilinx.com/cpld/index.htm.

If you need something more substantial on these features, an excellent application note exists at www.xilinx.com/bvdocs/appnotes/xapp378.pdf.

With these innovative features and your imagination, design problems will seem more manageable and hopefully make your design more successful.

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