The new Xilinx® Spartan™-3E FPGA family reduces your total system cost in many ways, including new low-cost configuration memory options. You can now choose the configuration memory solution that best suits your specific application requirements. For configuration memory, you can choose between industry-standard, commodity serial peripheral interface (SPI) or parallel NOR flash PROMs, competitively priced Xilinx Platform Flash, or other low-cost memories with a microcontroller.

Nearly all of the Spartan-3E configuration pins become available as user I/Os after configuration. Consequently, you can leverage any remaining space in the configuration memory for application data, such as code for an embedded MicroBlaze™ processor, serial numbers, or Ethernet MAC IDs. SPI and parallel flash PROMs additionally offer random-accessible, byte-addressable, read/write memory. If the application requires additional space, upgrade to the next larger PROM. Most SPI and parallel flash PROMs are available in a common footprint across multiple densities.

Xilinx Platform Flash still provides an excellent solution for stand-alone two-chip programmable logic solutions (FPGA + dedicated configuration PROM), with competitive cost-permegabit pricing. Platform Flash also excels with features such as JTAG in-system programmability and patented compression technology.

SPI flash PROMs are popular in high-volume consumer electronics applications, where they store system parameters or code for an embedded processor. SPI flash PROMs also offer a low-cost pin-saving configuration solution for Spartan-3E FPGAs. SPI flash memory is multi-sourced and multiple densities are available within the same package footprint.

Parallel NOR flash is the preferred solution for FPGA applications with an embedded processor such as the MicroBlaze soft-core processor. At power-on, the FPGA configures from one end of the parallel flash. After configuration, the MicroBlaze processor either executes directly from the opposite end of memory or shadows the code to external SDRAM.

What is SPI?
The serial peripheral interface (SPI) interface is a four-wire synchronous interface (Figure 1). SPI was originally pioneered as a serial communications interface between CPUs, MCUs, peripherals, and other devices supporting this protocol. Now SPI is popular in the embedded processing and consumer electronics markets. Many modern microcontrollers use this interface, as well as a wide variety of third-party peripherals.

SPI Flash Suppliers
Although SPI is a standard four-wire interface, the various available SPI flash PROMs use different command protocols. Spartan-3E FPGAs support up to four different command protocols. Currently, SPI flash PROMS from five vendors (Atmel, NexFlash, Programmable Microelectronics Corporation [PMC], Silicon Storage Technology [SST], and ST Microelectronics) are tested and supported, as shown in Table 1. Devices from other SPI suppliers are being tested and will be supported in the near future.

Memory Requirements
A single Spartan-3E FPGA requires roughly 600K to 6M bits for configuration, a small amount of memory relative to the large SPI capacities available today. Table 2 lists the amount of configuration memory required by each Spartan-3E device type, the minimum required SPI device size, and the extra memory that is available for other purposes. Note that it is not necessary to have a dedicated configuration memory device for each FPGA.

Multiple FPGAs can share a single SPI flash PROM in a configuration daisy chain.

Interfacing to SPI
Figure 2 shows the typical connections between a Spartan-3E FPGA and SPI flash memory, as well as the FPGA I/O pins used to control the configuration procedure. When the FPGA is in SPI flash configuration mode, three dual-purpose pins, called VS[2:0], define the type of attached SPI flash and operate as follows:

• These pins are only activated in SPI configuration mode (M[2:0]=“001”)
• The VS pins are sampled when INIT_B goes high
• The VS pins are reusable as user I/O after FPGA configuration completes (DONE goes high)

After Configuration
After configuration, all of the pins connected to the SPI flash PROM are available as user I/O pins. If not using the SPI flash PROM after configuration, drive the FPGA’s CSO_B pin high to disable the PROM, freeing the FPGA’s MOSI, DIN, and CCLK pins as user I/O.

If large enough, the SPI flash PROM can also contain non-volatile application data, such as MicroBlaze processor code or data such as serial numbers and Ethernet MAC IDs. Figure 3 shows an example of using SPI flash memory for multiple purposes.

Third-Party Peripherals
In addition to flash memory, many peripherals utilize the same SPI. These include:

• Memories (EEPROM, EPROM)
• Analog-to-digital converters (ADCs)
• Digital-to-analog converters (DACs)
• Thermal management
• Display drivers
• Microprocessors, microcontrollers (MCUs), and digital signal processors (DSPs)
• Many application-specific standard products (ASSPs)

Parallel NOR Flash
Spartan-3E FPGAs also provide a parallel configuration interface, primarily designed to configure the FPGA from industry-standard parallel NOR flash. The FPGA’s asynchronous memory interface is flexible and can connect to a variety of memory devices such as EEPROM, OTP EPROM, masked ROM, NVRAM, or even asynchronous SRAM.

The memory requirements are fairly simple. During configuration, the FPGA provides up to 24 address lines and receives byte-wide data. The FPGA has four control lines driving the memory’s chip-select, output-enable, write-enable, and an optional byte-enable for highdensity flash PROMs with a x8/x16 mode control (BYTE#). The memory must be 3.3V, 2.5V, or 1.8V and must have a read access time of 200 ns or faster.

Conclusion
In addition to low device costs, the new lowcost Spartan-3E FPGA family lowers overall system cost in many ways, including new support for inexpensive SPI and parallel flash memory for configuration. Currently, a number of flash memory families are supported and more memory vendors will announce their support for Spartan-3E devices in the coming months. Please check the Spartan-3E pages on the Xilinx website for a current list of supported SPI flash, www.xilinx.com/spartan3e/. Printable PDF version of this article with graphics.  (4/18/05) 295 KB