In the last few years, the Optical Internetworking Forum’s (OIF) system packet interfaces (SPI) for 2.5 Gb/OC-48 (SPI-3) and 10 Gb/OC-192 (SPI-4.2) have become the de-facto standards on all leading framer ASSPs. The SPI interfaces have also permeated into the network processor’s space, including next-generation processors such as Intel’s IXP2800 and IXP2400. Although these interface standards have been widely adopted, they pose significant design challenges to the system architect under pressure to deliver a fully compliant solution where time to market is paramount. Xilinx® Virtex™-4 architectures provide an ideal platform for implementing these multi-gigabit system packet interface applications.

Virtex-4 devices, combined with the portfolio of Xilinx pre-engineered IP solutions, are enabling system designers to build next-generation products faster than ever. Often these products involve bridging between multiple protocols, an application perfectly suited for FPGAs.

Figure 1 illustrates two examples of common bridging applications. The first FPGA bridges four SPI-3 (PL3) interfaces into a single SPI-4.2 interface, leveraging existing framers while also enabling support for the popular Intel IXP2800 network processor. The second FPGA bridges the SPI-4.2 interface to a backplane using the Virtex-4 embedded multi-gigabit transceivers. The Virtex-4 FX family supports a wide range of backplane applications, including PCI Express, XAUI, and Aurora.

To aid you in the development of your bridging applications, Xilinx provides a suite of application notes and reference designs. Leveraging the demonstration boards provided by Xilinx and its partners, you can complete these designs in hardware in a matter of hours or days, not weeks or months. Available under “Application Notes” at www.xilinx.com/support/library.htm, they include:

• Gigabit System Reference Design (XAPP 536)
• Gigabit Ethernet Aggregation to SPI-4.2 with Optional GFP-F Adaptation (XAPP 695)
• Mesh Fabric Reference Design (XAPP 698)
• Gigabit Ethernet to Aurora Bridge (XAPP 777)
• SPI-4.2 to Quad SPI-3 Bridge (XAPP 525)

SPI-4.2 to Quad SPI-3 Bridge
The outline of the SPI-4.2 to Quad SPI-3 bridge design is illustrated in Figure 2. This design not only converts electrical interfaces between SPI-3 and SPI-4.2, but also includes data buffering and width conversion, arbitration, and flow-control management.

For the dataflow from the SPI-3 to SPI- 4.2 interface, the bridge accumulates multiple streams of data (as many as four different SPI-3 interfaces) and generates a single output stream of SPI-4.2 data. A programmable amount of data is stored in each channel, and flow control from the SPI-4.2 interface determines the amount of data to transfer on each channel. Simple round-robin arbitration is implemented, but can easily be enhanced to provide more complex algorithms based on your system requirements.

In the SPI-4.2 to SPI-3 direction, the bridge de-multiplexes a single SPI-4.2 interface into individual channels, generating four separate SPI-3 output streams. A programmable amount of data is stored in each channel, and flow control from the SPI-3 interface determines the amount of data to transfer on each channel.

The reference design provides all of the required design files (in both VHDL and Verilog) to implement the bridge logic between the four SPI-3 cores and the SPI-4.2 core. The design supports a suite of parameters to customize the design based on user requirements. These include:

• FIFO thresholds to determine flowcontrol information
• Additional device/package information
• Static and dynamic alignment configurations of the SPI-4.2 core
• Configurable FIFO depths

System designers creating bridging applications outside of this SPI-3 to SPI-4.2 application will also find this reference design highly valuable. Per-channel data buffering, arbitration, and flow control are some examples of the features implemented by this bridge. The channelized FIFOs are created by the Xilinx FIFO Generator, which supports a suite of features including non-symmetric aspect ratios and first-word fall-through (FWFT). Non-symmetric aspect ratios enable easy width conversion between different data widths, and FWFT provides the ability to look ahead to the next word available from the FIFO without issuing a read operation. For more details on the FIFO Generator, see “Never Design Another FIFO,” also in this issue of the Xcell Journal.

IP Core Solutions
The SPI-3 and SPI-4.2 cores require high-speed I/O operation and tight timing to meet the OIF specifications. These cores easily meet these requirements through Virtex-4 ChipSync™ technology, enabling the use of the embedded I/O SERDES and dynamic phase alignment. This greatly alleviates the design complexities for SPI users, enabling them to focus on their system requirements instead of the SPI interfaces.

The SPI solutions are delivered through the CORE Generator in standard IP releases, and provide immediate simulation capability at no cost. You can also obtain a hardware evaluation license, which enables the SPI cores to be downloaded into hardware for full system evaluation. The cores will timeout after a couple of hours, enabling full hardware evaluation in your application.

The suite of SPI IP includes the SPI-4.2 for OC-192 applications and the SPI-3 Link, SPI-3 PHY, and SPI-4.2 Lite for OC-48 applications. The SPI-4.2 and SPI-3 IP provide simple out-of-the-box solutions for these complicated interface protocols.

SPI-4.2 and SPI-4.2 Lite Cores
The Xilinx SPI-4.2 IP is a fully verified, plug-in SPI-4.2 interface solution. It provides you with a wealth of configuration options to tailor the core for your specific design requirements, including the ability to operate at data rates exceeding 1 Gbps using dynamic phase alignment.

In addition to the SPI-4.2 full-rate core, Xilinx also provides the SPI-4.2 Lite core. The SPI-4.2 Lite IP leverages the efficiency of the SPI-4.2 interface for slower OC-48 applications. It is fully compliant to the SPI-4.2 OIF specification, except that it operates at a maximum frequency of OC-96 (5 Gbps), but requires less than 50% of the resources of the full-rate SPI-4.2 core.

SPI-3 PHY and Link Cores
The Xilinx SPI-3 Link and PHY cores provide complete solutions for your OC-48 applications, and support a suite of options to customize the cores to meet your application needs. Both the SPI-3 Link and PHY cores support not only a 32-bit interface, but also 8- and 16-bit interfaces for interfacing to a suite of framers and network processors. Previously available as fixed-point solutions, the SPI-3 PHY and Link cores will be released in ISE™ 7.1i IP Update 3, available in Q3 2005.

Conclusion
Xilinx IP and reference designs provide superior solutions for implementing custom bridging solutions between protocols. You can use the XAPP525 bridge design out of the box for SPI-4.2 to quad SPI-3 bridging applications or for any system that requires channelized buffering, arbitration, and flow control using system packet interface protocols. In addition, the SPI cores provide fully compliant, drop-in solutions for these complicated interfaces. The SPI solutions alleviate design challenges and result in faster time to market for Xilinx customers. The low cost and full feature set of the Virtex-4 family, combined with the suite of SPI IP and multi-gigabit bridge designs, provide an unbeatable combination.

Although we highlighted only the SPI IP in this article, Xilinx has a wealth of IP solutions for all of your connectivity and bridging needs. For more information, please visit Connectivity Central in the IP Lounge at www.xilinx.com/products/design_resources/conn_central/index.htm.

For more information regarding the SPI-4.2 core and its benefits in the Virtex-4 architecture, please refer to the following article from a previous edition of the Xcell Journal: www.xilinx.com/publications/xcellonline/xcell_52/xc_v4spi52.htm.

For more information about the SPI-4.2 and SPI-3 IP solutions, visit www.xilinx.com/xlnx/xebiz/designResources/

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