A few months ago, I needed a few new hard drives: two desktop drives for home and a bigger 120 GB drive for my laptop, which was out of space. Browsing through a Seattle-area computer store, I compared the prices of Ultra ATA drives (older, parallel architectures) and Serial ATA (SATA) disk drives, discovering that the higher throughput of the SATA drives had resulted in price points that were twice those of the Ultra ATA drives. To me, this presented a crisp picture of the economic drivers behind the SERDES technology wave: higher throughput commanding a higher price, yet lower manufacturing costs.

You would think hardware designers would be making a mad dash toward serial design. However, I find that the “dash” toward SERDES seems to hover around 20 percent. Pondering this, I have come to believe that there are three primary reasons for the reticence among the remaining 80 percent:

1. Speed. Many applications are not pushing the speed envelope.
2. Resistance to change. Even innovative engineers are creatures of habit. 3
3. Real or perceived technical hurdles. SERDES design requires a different approach than wide, parallel bus design.

In this article, I’ll address the third reason in detail. Although my focus is on Xilinx® Virtex™-II Pro RocketIO™ technology, the information would apply to any serial interface, including RocketIO transceivers in Virtex-4 devices.

Line Loss
An ideal lossless transmission line assumes that a signal propagates down the line with no energy loss. In other words, if a 1.0V signal with a 1.0 ns rise time enters one end of the line, the same 1.0V and 1.0 ns signal will come out the far end.

This is a good approximation when signal rise times are on the order of 1.0 ns (or slower), and with trace lengths of 10 in (or shorter). However, as rise times trend toward 100 ps and lengths get significantly longer (as in a backplane), the lossy effects of transmission lines begin to influence signal quality dramatically. As Figure 1 shows, these effects – both attenuation and risetime degradation – vary directly with length at higher frequencies.

To describe and accurately predict the behavior of real interconnects, two important mechanisms that absorb energy from the signal must be modeled:

• Resistive loss. From DC through frequencies up to a few megahertz, the current in a trace moves through the entire cross-sectional area of the trace. At higher frequencies, however, current flows along the perimeter of a line rather than uniformly across the entire cross-section. As a result, the series resistance of the signal and return path conductors increases with the square root of frequency as the effective crosssection of the interconnect path is reduced. Resistive loss is also referred to as “skin effect.” But no matter what you call it, it is the same phenomenon, and something you should be concerned about at high frequencies.
• Dielectric loss. The second important loss mechanism is dielectric loss, which is simply the conversion of electrical energy from the alternating electric field into heat. Dielectric loss, often specified in decibels per meter, increases with frequency and varies inversely with a material’s “loss tangent” – a function of the material’s resin type and molecular structure. Depending on resin content, “vanilla” FR-4 has a loss tangent ranging from 0.02-0.03. Lower loss tangent equates to more of the output signal getting to its destination, as well as higher material costs compared to FR-4. GETEK, for example, has a loss tangent of 0.012. Nelco 4000-13 is 0.01. And the loss tangent for Rogers 4003 is as low as 0.0027. For an actual design, you will want to discuss the tradeoffs with your board vendor.

Loss, Jitter, and ISI
I’ve often heard engineers use the terms inter-symbol interference (ISI), jitter, and loss to refer to the same thing: the unknown cause of a less-than-optimal signal or bitstream. In fact, these are different phenomena.

Random jitter is used to describe random events that result in a delay between the expected and actual signal transition. The distribution of random effects follows a classic Gaussian distribution, where the results vary wider (in time) as more data is observed. This data is typically provided by the driver manufacturer.

Deterministic jitter encompasses the list of systematic interconnect effects that will reoccur if you repeat the same stimulus. Dielectric and resistive loss, as well as crosstalk, reflections, via parasitics, returnpath discontinuities, and any systematic aspect of an interconnect design contribute to deterministic jitter.

If the combined effects of random and deterministic jitter are significant enough, ISI will result, indicating that bit distinctions have become “blurry” at the receiver. This becomes particularly serious when rise-time degradation becomes comparable to the bit period of the signal. As a result, the shape of the received waveform will depend on the prior bit pattern (ISI).

These effects are best modeled using an oscilloscope that supports eye diagram analysis. Eye diagrams provide a visual display of the signal quality over many bit transitions with both deterministic and random jitter serving to close the “eye.”

At a glance, an eye diagram will show if an interconnect is acceptable. Pass/fail criteria are often specified by an eye mask, shown as a blue hexagon on the left-hand side of Figure 2. Eye masks, which conform to the various SERDES specifications, define minimum and maximum keep-out regions where proper bit transitions should not appear for proper receiver interpretation of the driver’s intent.

Typically used bit patterns, or “pulse trains,” include 8b/10b encoding and PRBS (pseudo-random bit stimulus). The 8b/10b data transmission scheme is considered ideal for high-speed local area networks and computer links. Realistic, long character sequences eventually hit some kind of worst-case history, but this can take a long time. A PRBS stimulus, as shown on the right-hand side of Figure 2, provides a means to force as much “action” on a serial data path as possible, in the smallest number of cycles. It is “pseudorandom” because it actually repeats after a pre-determined “n” number of bits.

Losing Less from Lossy Lines
Assuming that you have followed good routing rules (for example, achieving a consistent differential impedance of 100 ohms and avoiding excessive routing skew), there are five major ways to mitigate loss:

1. Reduce resistive loss by widening traces. Because resistive loss or “skin effects” are the result of a reduced cross-sectional area in a trace, wider traces result in a larger cross-sectional area, so the percent reduction due to resistive loss becomes smaller.
2. Reduce dielectric loss by shortening lines. Dielectric loss is a function of the material used and the length over which a signal is transmitted. Shortening the overall interconnect length (which may not be possible in many systems) can be an effective means of eliminating loss.
3. Reduce dielectric loss by employing lower loss tangent dielectrics. To reduce dielectric loss, more expensive materials – with lower loss tangents – can be considered, perhaps after exhausting less-expensive approaches.
4. Increase driver pre-emphasis. Boost the initial voltage level of each edge to compensate for high-frequency loss. (The trade-off here is additional power consumption.)
5. Equalization at the receiver. The incoming signal’s lower frequency components are intentionally attenuated to artificially balance between high- and low-frequency components. The result is then amplified, with equalization of the low- and high-frequency signal components.

The HyperLynx RocketIO Design Kit
In an effort to make multi-gigabit interconnect implementation as painless as possible, Xilinx and Mentor Graphics have teamed up to provide the RocketIO Design Kit for HyperLynx. Editable, pre-configured circuits in the kit are ready to simulate for both chip-to-chip applications and PCB backplanes – including connectors and pre-configured differential striplines.

The FR-4 traces used are a differential pair of centered striplines, 12 mils wide and 20 mils apart, with a 50 ohm characteristic impedance.

Figure 2 shows simulation results for the Xilinx backplane example with a 36 in transmission path and four vias. The eye in the figure shows encroachment on the XAUI (10 Gb Extended Attachment Unit Interface) eye mask when using 10 percent pre-emphasis. Here, we can clearly see the effects of ISI at the receiver.

Although you could engage any of the five primary loss-reduction mechanisms to open up the eye, let’s assume that the 36 in backplane is a design requirement and that the four vias are inevitable. One of the remaining options is pre-emphasis, which can be bumped up to 20, 25, or 33 percent. Figure 3 shows the results at 25 percent pre-emphasis: the eye is wide open, which is great. With the wide margin around the XAUI mask’s internal keep-out region, I would want to simulate this again at 20 percent pre-emphasis in an attempt to conserve power.

Conclusion
Although I simulated only one solution here, any permutation of the five ways to deal with loss is possible. Moreover, you could also examine non-ideal routing effects, including simulation of the impacts of differential length skew. With the availability of helpful simulation tools like HyperLynx, you don’t need to fabricate prototypes – wondering whether you’ve over-designed or under-designed, spent too much or spent too little.

In a future extension of this theme, we’ll revisit the Xilinx SIS Kit backplane design and examine the impact of the new equalization technology in the Virtex-4 implementation of RocketIO transceivers.

The HyperLynx RocketIO Design Kit is available from www.mentor.com/hyperlynx.

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