The problem of signal integrity is a lot like trying to carry on a conversation at a crowded trade show. If you and the person you’re talking to are in a quiet corner of the hall with some nice padded walls around you and not too many other people nearby, it isn’t a problem. Try the same conversation in the middle of the exhibit floor with hundreds of people all around, noise from neighboring exhibit booths, and no walls to break up or absorb the sound, and you’ve got a problem.

Back in the good old days of logic design, we didn’t give much thought to signal integrity. We had 5V power supplies, DIP packages with leads that actually went through the board, and high-speed microprocessors running at a heady 5 MHz.

If you paid a little attention to board layout and put a decent ceramic bypass capacitor next to each chip, you probably didn’t have to worry about your signals. Ones stayed ones and zeroes stayed zeroes. Even 100 mV of noise on a signal wouldn’t be enough to change its logic level.

Today, designers are caught between design requirements for ever-increasing bit rates, faster edge rates, higher clock speeds, and technology advances that keep lowering operating voltages, reducing package sizes and ball pitch, and forcing more components into a smaller amount of board area.

Signal Integrity Today
Take a look at present-day source-synchronous interfaces. DDR and QDR memory interface speeds are rapidly increasing, with DDR2 speeds at more than 500 Mbps. The bit rates are getting faster and the buses getting wider. With faster bit rates comes faster edge rates, which now can be just a few hundred picoseconds.

Faster is better, but there are a few hurdles to deal with. Parasitic inductance and capacitance – which didn’t matter a whole lot at lower speeds – are suddenly very important. The resulting noise because of the parasitics is a big concern. Today it is common to have FPGAs with hundreds of I/Os switching, causing high levels of simultaneous switching output noise (SSN). This affects your system in many ways, especially causing jitter, which can reduce your timing margin or even cause system failure.

You cannot allow yourself to ignore signal integrity and gamble that your system will work as designed. You might be forced to reduce the clock rate just to get the system to work, or be forced into a complete board re-design to correct signal integrity issues.

What Kind of Integrity Do You Have?
Having good signal integrity usually means controlling unwanted noise on logic signals. Noise usually falls into one of two main domains:

• Level-related noise affects the logic level of the signal. If the noise is large enough, the signal may cross the threshold from a desired logic state to an undesired state and propagate into other logic.
• Time-related noise, or jitter, affects the position of a signal transition and causes setup/hold windows for data sampling to be violated, thereby allowing incorrect data to be sampled and propagated through the system.

Controlling Noise
A well-designed package is critical to signal integrity. Noise can emanate from many sources in a system. If the noise source is on the board, there are some potential solutions once you find out where the problem is (probably after a long and laborious debug process). If the problem is in the package, you have little or no choice but to change the design, vendor, or parts. This is a time-consuming process that can affect product revenue significantly. For this reason, it is imperative to have a well-designed low-inductance package.

When speeds were still fairly low, short signal paths did not alter signal characteristics. Today, with rise times in the hundreds of picoseconds (even if bit periods are a few nanoseconds), the frequency components of signals run into gigahertz, causing even very short signal paths like package traces to impact signals.

For every signal line, there is an associated return path for the return currents. For single-ended signals, these return paths are usually GND or VCC reference planes. To maintain a 50 ohm line, the returns should be in close proximity to the signal.

Although PCB traces are less of a concern, you must pay close attention to vias. For large FPGAs the breakout region – the area between the package balls to the PCB – is extremely critical, as it comprises a dense concentration of signal vias.

SSN is generally observed as “ground bounce” and can be caused by two different phenomena.

First, noise because of via-field crosstalk is a function of loop inductance, which is a function of the proximity of ground/power reference pin locations to the signal pin. Signal pins farther away from a reference pin are more susceptible to noise. This problem is exacerbated when a number of I/Os in the region switch simultaneously. Proper distribution of ground/power and signal pins in a package is extremely critical – in other words, a good pinout architecture.

Second, maintaining a clean power supply to the FPGA is also critical to maintain acceptable signal integrity. Noise margins are reduced as VCC values drop down to 1.2V.

Furthermore, any noise in the power rail translates to jitter at the output, shrinking available timing margins. As noise depends on package inductance and the number of simultaneously switching I/Os, optimal signaling requires a good low-inductance package.

Tackling the SSN Challenge
One package that tackles the SSN challenge is the Xilinx® Virtex™-4 FPGA package. Most notably, the package enables better noise performance on higher speed single-ended interfaces, which are more susceptible to noise than differential interfaces such as LVDS. The pinout architecture of the package is responsible for roughly 80% of the total noise. The Virtex-4 FPGA package achieves optimal pin distribution through a tiled pattern – a regular array of signal, ground, and power pins called SparseChevron pinout (Figure 2).

The signal-to-ground-to-power ratio of the package is 8:1:1. Because both power and ground are equally effective as return current paths, the package effectively has a signal-to-return ratio of 4:1. Also, the pins are distributed so that every signal pin is adjacent to a return pin, ensuring that the return current loop is kept to a minimum.

Additionally, the abundance of return paths in any given area of the package provides a low impedance path for the return currents. The pinout also confines noise from an aggressor to a smaller area so that the influence of the aggressor drops rapidly with distance. Because crosstalk noise is cumulative, this results in a lower total SSN.

Simplifying Signal Termination
On-chip termination (active termination) removes external components and places termination closest to where it matters (driver or receiver).

To maintain the ideal 50 ohm line impedance, it is normal design practice to have termination resistors on each signal. For hundreds of signal I/Os, this can translate to many hundreds of external termination resistors. The physical challenges of placing the resistors on the board and their connections to the power and ground planes are not trivial.

The Xilinx Controlled Impedance Technology (XCITE) on-chip active I/O termination used in Virtex FPGAs solves many of the problems associated with signal termination. XCITE provides both parallel and serial equivalent options for single and differential termination. Impedance is controlled using an internal reference voltage and is available on all I/O pins. This active termination provides automatic temperature and voltage compensation; puts the termination inside the buffer circuitry where it belongs; and saves board space and cost by eliminating hundreds of discrete resistors. Figure 3 shows the simplified board layout and signal trace paths using both conventional and Xilinx XCITE DCI termination technology.

Power Plane Integrity
Power and ground planes are important to maintaining signal integrity in FPGA designs. To maintain the characteristic impedance (Zo) across the frequency range of interest, reference planes for single-ended signals should be very low impedance.

Otherwise, the result is impedance discontinuities, causing jitter due to reflections. In addition, noisy power and ground planes affect circuit performance on the die, causing additional jitter. It is important to design packages with continuous power and ground planes to minimize impedance.

Typically, PCB designers use decoupling capacitors to filter out noise and maintain a clean power supply. For reducing high-frequency noise, decoupling capacitors are placed close to the noise source. Leadingedge ASICs and FPGAs are equipped with very low-inductance decoupling capacitors within the package to aid cleaning the power-supply noise.

Compensating for Signal Integrity Issues
Improving the signal integrity of your system will enhance the data valid window (the eye) of the high-frequency signals reaching your FPGA I/O pins. However, this is only half the battle. Even superior designs exhibit shrinking data valid windows, as shown in the 533 Mbps DDR2 SDRAM example shown in Figure 4. The input circuitry needs the capability to capture the data by centering the clock to the middle of the shrinking data valid window.

Virtex-4 FPGAs have unique ChipSync™ technology built into every I/O block that makes data capturing easier and more reliable. It includes a precision delay called IDELAY that generates the tap delays necessary to center data to the FPGA clock. Memory strobe edge detection logic, included in the I/O block, uses this precision delay to detect the edges of the memory strobe from which the pulse center can be calculated. Delaying the data by the number of delay taps counted between the first and second edges aligns the center of the data window with the edge of the FPGA clock output. The tap delays generated by this precision delay block allow alignment of the data and clock to within 75 ps resolution.

ChipSync technology also simplifies the design of differential parallel bus interfaces, with embedded SERDES blocks that serialize and de-serialize parallel interfaces to match the data rate to the speed of the internal FPGA circuits. Additionally, this technology provides per-bit and per-channel de-skew for increased design margins, simplifying the design of interfaces such as SPI-4.2, XSBI, and SFI-4, as well as RapidIO.

Conclusion
Signal integrity is a key issue in today’s high-speed designs and will continue to be important as more high-speed signals are squeezed into smaller amounts of board space, packages get denser, and ball spacing shrinks.

Signal integrity issues can affect voltage and time domains, combining to reduce the window of available valid data in a system. If the issues become large enough, systems may not work at all or be extremely unreliable, forcing long and costly system redesigns.

It might never be possible to completely eliminate signal noise in a high-speed system. But paying attention to several key areas can minimize noise or adjust timing so that system performance is not compromised. These include using well-engineered, low-inductance packages; using devices with built-in power supply decoupling; using active signal termination where necessary; and choosing devices with the ability to adjust the relationship between the data valid window and the clock.

For more information, visit www.xilinx.com/signalintegrity.

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