Digital designers have long reached for an oscilloscope for debug. As FPGAs have become the centerpiece of digital design, the need to quickly debug systems that include programmable logic is stronger than ever. However, traditional oscilloscope technology has not kept up with the functional debug of FPGAs. A new breed of oscilloscopes known as mixed-signal oscilloscopes (or MSOs for short) delivers vital capabilities if you are developing systems with FPGAs.

Like traditional oscilloscopes, MSOs offer the same rich feature set for taking parametric measurements to measure signal integrity, jitter, and signal characterization. You can choose between versions that have either two or four analog input channels. MSOs come in a variety of bandwidths ranging from 300 MHz to 1 GHz bandwidth; these capabilities are important for checking signal parametrics. For example, you can readily change I/O standards and drive strengths using Xilinx® FPGA Editor and measure the real-world I/O characteristics using an MSO’s scope channels.

The major difference between MSOs and traditional DSOs (digital storage oscilloscopes) is the addition of 16 digital asynchronous sampling channels on the MSO. Plus, you can choose how fast these digital channels sample. The digital channels offer deep memory storage independent of the analog channel memory storage. You can employ the capabilities of the digital channels in a number of different ways that are particularly valuable for developing systems that incorporate FPGAs.

Bus Triggering and Display
Traditional oscilloscopes provide digital triggering capabilities that allow them to trigger on patterns across analog channels. With a four-channel oscilloscope, you can trigger on a single pattern that is as wide as four signals.

Debug often requires looking at buses using a specific event as the trigger condition. Using an MSO’s digital channels, you can trigger on a digital pattern as wide as 16 signals. This can be a powerful capability if you need to look at a state machine, an embedded microcontroller, or a data bus. In addition, you can also trigger and capture measurements across all four analog channels, extending the trigger width up to 20 signals, as shown in Figure 1.

Correlating Analog and Digital Measurements
Although you can use the digital channels to make strictly digital measurements, their capabilities are best employed for looking at problems that are both functional and parametric in nature – for example, triggering on a digital bus and having this trigger condition arm the scope measurement.

At Agilent, one of our design teams experienced an infrequent software glitch on an embedded product under development. This anomaly manifested itself very infrequently – about once a week. The software team developed diagnostics that caused the problem to happen on a more frequent basis. With this diagnostic software, they found that the problem occurred during read cycles on a PCI bus embedded in an FPGA.

The team routed PCI status signal out to pins and connected the MSO’s digital channels to these signals. Engineers quickly set up the MSO digital trigger on a PCI read cycle and then set the MSO scope channels to acquire when the MSO digital channels recorded a PCI bus read cycle.

With the ability to trigger on a specific bus cycle, the team was quickly able to resolve the problem. They found a clock with a too-slow rise time that impacted primarily read cycles. The team modified the design and downloaded a new configuration file into the FPGA. The combination of reprogrammable FPGAs and MSO measurements allowed the design team to fix the problem and ship the product on schedule.

Extensive Internal Visibility
To access internal signals, you might typically use the route-out approach to bring signals to pins that can be probed using an oscilloscope. Using traditional oscilloscopes, you would have access to either two or four signals at a time. This narrow signal visibility can complicate debug, as a number of problems require simultaneous visibility across a higher number of signals. To access new signals, you must change the design, re-synthesize, and run a new place and route to make your signals accessible to the oscilloscope. This process can take hours.

With the digital channels of an MSO, you have visibility of as many as 16 internal FPGA signals at a time. The power of the MSO’s digital channels can be further extended when combined with on-chip technologies such as the Xilinx ChipScope™ Pro tool and Agilent FPGA Dynamic Probe.

The ChipScope Pro analyzer allows design teams to incorporate an Agilent debug core in their FPGA designs. The debug core, known as ATC2, provides an easy way to route signals to pins, enables a faster setup of the MSO, and allows you to quickly measure new groups of internal signals. This capability extends the reach of the 16 digital channels into the FPGA design.

Let’s look at a simple communication system to illustrate the value of an MSO’s digital channels for FPGA debug. A state machine drives the process of sending out packets of 16-bit data along with a transaction ID. Parallel data is serialized, sent on a serial channel, de-serialized, and brought into a monitor. A second state machine at the monitor drives the process of receiving the packets and strips off the data and transaction IDs so that the packets can be pulled off to external memory. This state machine also generates acknowledge IDs that are fed back to the transmit side to communicate that data was received. The design originally dedicated 16 pins for a debug port.

Using the ChipScope Pro core inserter, you can parameterize an ATC2 core. A benefit of the core inserter is that you need not modify the original HDL design, as core insertion occurs post-synthesis and before place and route. You would simply specify, using the core inserter, which internal signals to group together as an active signal bank. Place and route uses the original user constraint file, so no additional work is required.

The core inserter also produces a small file that contains the specified signal names and groups. This file, known as a .cdc, is read by the FPGA Dynamic Probe application running on the MSO. When changing which signal group is presented to the MSO, the instrument automatically uses this signal naming file to correctly update signal names on the display. As opposed to the route-out approach, which can take hours to bring new signals to pins, the FPGA Dynamic Probe allows you to access a new group of internal signals in about one second.

For fast debug, the design team needed visibility into four sections of the design. The designer thus created a core with four signal banks to give access to 64 signals, 16 at a time, over the 16-pin debug port (as shown in Figure 2). ATC2 cores can be parameterized to have as many as 64 signal banks, providing access to 1,024 internal signals with the MSO’s 16 digital channels.

Timing Cores
You can configure ATC2 cores as either timing (asynchronous) or state (synchronous) cores; both types of cores are supported with the MSO. The core inserter injects a core into a design post-synthesis and before place and route. If you specified a timing core, the place and route tools do not put any flops between the signal being probed and the output pin; the routing of the signal to pin for measurement is treated as a false path. This allows the place and route tools to ignore any speed constraints associated with routing a specific signal to a pin.

The timing core does include a JTAG controller, but the controller typically runs very slowly (<5 MHz), as it is only used for small information exchanges such as selecting a new signal bank. Timing cores can be effective, as they allow you to look at signals across multiple clock domains or at anomalies that have a duration of less than one clock cycle. The primary trade-off associated with timing cores is that skew will exist between signal paths.

State Cores
Traditional oscilloscopes as well as MSOs provide asynchronous acquisition. Samples are stored using an adjustable clock reference internal to the scope. This can make it difficult to accurately capture and decipher synchronous events as the instrument captures invalid transitions between clock cycles.

A more effective way to capture synchronous information on a single clock domain is to parameterize the ATC2 core as a state core. A state core will have minimal impact on design timing because of its pipelined architecture. A total of four flops are placed between the signal being probed and an output pad (Figure 3). The design tools place the first flop as close as possible to the signal being probed. The additional three stages of pipelining allow the signal three clock cycles before reaching the output pad. The pipelined architecture of the ATC2 core allows the place and route tools to have a much greater probability of meeting the original timing goals of the design.

As the core is synchronous, the place and route tools eliminate skew between signal paths. The primary trade-off with a state core is that it works with a single time domain. Using the state core approach, you can measure across clock domains by inserting multiple state cores. The MSO can access multiple ATC2 cores, one at a time, in a single FPGA or distributed across multiple FPGAs on a single scan chain.

The MSO’s digital channels provide exclusively asynchronous acquisition. For FPGA debug, a method exists for allowing the MSO to display synchronous measurements, even though the initial acquisition occurs asynchronously. The ATC2 state core outputs a clock signal and signal states synchronous with the clock. The MSO’s digital channels acquire this pre-formatted state information. Then the MSO post-processes this measurement using a state display feature that allows you to specify one signal as the clock. The MSO filters out to all transitions between valid states. This makes it possible to make synchronous measurements internal to the FPGA.

Conclusion
The reprogrammable nature of FPGA technology makes rapid iterative real-world debug a great companion to simulation. As FPGAs become even more sophisticated, the need for efficient internal visibility increases. Mixed-signal oscilloscopes provide unique measurement capabilities that align with the needs of those designing systems that incorporate FPGAs. Applications that help you exploit the digital measurement capabilities of MSOs are a catalyst for shorter development cycles and higher quality designs.

For more information about the FPGA Dynamic Probe for Agilent MSOs, visit www.agilent.com/find/msoFPGA.

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