FPGAs were once used in smaller, simpler applications. A small team could create designs that reached desired performance levels with some HDL knowledge and minimal FPGA fabric experience. With larger densities, ever-increasing features, and threatening competition, new design techniques are necessary to predictably achieve maximum device performance and shorten development time.

You can apply some of these new design techniques by using constraints within Xilinx® ISE™ software, entering constraints using several tools (or manually with a text file). These older methods work, but the chance of making a mistake is high. Each time you make a modification using these traditional tools, you are forced to wait for another place and route (PAR) run. In the end you might find out that the changes were ineffective, and now you are stuck in an endless loop trying to close on timing.

With enough effort and iterations, you will eventually have an idea of what it takes to achieve timing closure. But how much time will you need – and how many iterations will be required – before you get the design and constraints to converge on timing? Is it a matter of refining the constraints, placement, or changing the RTL structure?

When using a flat methodology to make even minor changes to a given logic block, you must redo PAR for the entire design. This adds up to a significant amount of wasted time, as 50 or more PAR iterations – at 8 or more hours apiece – are common with today’s larger FPGA netlists.

The PlanAhead QuickStart! service delivers individualized service that includes a QuickStart! application engineer at your site for a week. This Xilinx expert will train design teams on the PlanAhead™ hierarchical design environment, which allows designers to create block-based incremental designs, run timing analysis, reduce PAR times, create reusable modules, and group fabric for optimal routing and consistent results. After a two-day training course on PlanAhead design tools, the QuickStart! engineer will then provide support and consultation customized specifically to address your design requirements.

Benefits of Floorplanning
Two important but opposing features of a great design are obtaining maximum speed and minimal device utilization. A design with a highly optimized HDL netlist can still fail to meet timing with non-optimal logic placement. Each time a design undergoes PAR, the internal logic can move or shift because placement is not predictable. As a result, performance can change dramatically with each PAR run. Synchronous elements placed in a scattered fashion can slow timing because of routing delays, but these can be dramatically reduced – and device utilization minimized – by closely grouping the related logic. Timing-driven floorplanning helps you reach the highest speeds while using a minimal amount of FPGA fabric, saving more fabric for extra features and options.

Benefits of Hierarchical Design
The PlanAhead QuickStart! service rapidly enables design teams to utilize a hierarchical design methodology and increase design performance. This methodology enables the design to be broken up into separate hierarchical blocks or modules. Once PAR is locked in for each block, placement and routing between the blocks is performed. The less routing delay between the internal sub-modules of a block and between blocks, the more predictable timing closure is for the overall design.

Each separate block can undergo PAR by different team members. They will also have the control to make changes to their blocks independently of their teammates. Instead of making changes to the design as a whole, individual team members can make small incremental changes to portions of the design. This approach increases productivity because it reduces the total number of time-consuming PAR runs. The modular design flow also reduces the time needed for each PAR run. Isolating the problem to specific block(s) eliminates the extra PAR iterations usually required when working with a flat methodology.

PlanAhead Design Tools
Historically, it was difficult to follow hierarchical design methodologies with older FPGA design tools. Several software applications or design tools were needed at various stages in the design implementation. The hierarchical design planning capability of PlanAhead design tools includes an advanced user interface, making it easy to use. Multiple views highlight the resources, connectivity, and logical and physical hierarchy, enabling design teams to quickly inspect and rectify problem areas. They can also create and manipulate physical hierarchy independently from logical hierarchy. The tool is powerful and allows designers to simultaneously plan and analyze multiple physical implementations.

Benefits of PlanAhead QuickStart!
ASIC designers have been taking full advantage of hierarchical design methods for years. Now it’s time for FPGA designers to learn how to use the PlanAhead environment and follow new design techniques and requirements. The QuickStart! engineer will provide a two-day Designing with PlanAhead course, followed by three days of on-site customized support and consultation. The engineer will be familiar with PlanAhead fundamentals, as well as other design aspects that may need consideration. After a week of dedicated support, your team will be familiar with fundamentals of modular and block-based design, working at an expert level with the PlanAhead hierarchical design environment.

Conclusion
Many designers are comfortable with a push-button flow, which is defined by simply writing and synthesizing HDL and using Xilinx implementation tools without special options or design constraints. Most design teams can obtain desired results with this flow. But for designers creating powerful applications, floorplanning and hierarchical block-based design techniques are essential. The PlanAhead hierarchical design environment allows you to design with a new powerful methodology. The PlanAhead QuickStart! service enables you to reap the benefits in only a week.

To find out more about PlanAhead QuickStart!, contact your Xilinx representative or visit www.xilinx.com/paq.

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