Synplicity’s Synplify Pro software is a powerful synthesis tool that allows you to maximize Xilinx® Spartan™-3 resources. If you are using the Xilinx ISE™ tool suite to identify the critical paths, you can easily perform timing closure with Synplify’s constraint entry capabilities.

Synplify also has many synthesis directives to aid in the timing closure of your design. Using the capabilities of the Synplify Pro tool, you can achieve the best performance for Spartan-3 devices.

Setup
Our test case used Synplify Pro software (version 7.7.1) and Xilinx ISE software (version 6.3i) targeting a Spartan-3 XC3S50TQ144-4 FPGA. We used the default settings for the first synthesis and implementation run, as well as Synplify’s various synthesis options and its constraint editor, SCOPE.

Because we cannot access SCOPE within ISE software, we created separate Synplify and ISE projects. By using the same project directories for both the Synplify Pro project and the ISE project, the newly created EDIF and NCF files can be immediately available to the ISE tool. The NCF, which has the same syntax as a UCF, is made automatically from the constraints entered through the Synplify tool.

To make sure that the NCF gets used, we selected the Synplify Pro implementation option “Write Vendor Constraint File” on the implementation results tab. The NCF file has to have the same name as the EDIF file so that ISE software will automatically use it.

Modifying Default Settings
Running the design through the Synplify tool with the default settings gave a report with an estimated frequency of 163 MHz and an actual frequency after implementation of 115 MHz. The design was autoconstrained by Synplify Pro software to 191 MHz, which resulted in a 191 MHz period constraint in the NCF. We arbitrarily set a design goal of 190 MHz – so now we need to improve by 75 MHz.

This design has case statements that we can interpret as finite state machines. The FSM Explorer option is turned on, which explores different encoding styles for the state machines and decides on the best implementation. The retiming option allows the synthesis tool to move registers through asynchronous logic so that a more evenly distributed delay is achieved between registers. Selecting both of these synthesis options increased the synthesis-estimated speed of the design to 217.7 MHz.

In the majority of designs, overconstraining causes detrimental results. Without having specified a synthesis period constraint, the Synplify Pro tool auto-constrained the design to 267 MHz after the FSM Explorer and retiming options were selected. As this constraint is much greater than the estimated results, we used a constraint of 218 MHz in SCOPE (Figure 1).

Once the SDC file was created, we added it to the project. With the constraint now added, Synplify Pro software reports a speed of 219.2 MHz. A constraint of 220 MHz gives the same estimated result – 219.2 MHz.

Analysis
With the default settings in ISE software, we achieved a result of 164 MHz. This result is based off the period constraint that Synplify software passed into the NCF. Setting the PAR effort level to high gives a result of 166.7 MHz. Inspecting the report from Timing Analyzer, we see a common critical path through an instance called “s_”:

Floorplanner
With the help of Xilinx Floorplanner, we can determine the connectivity of “s_”. In Figure 2, “s_” is selected (yellow). The black lines represent its connectivity in relation to the other parts of the design. This instance is spread out, so an area group constraint is necessary. Instead of entering the area group constraint into a UCF, we entered the constraint SCOPE, which allows the Synplify tool to make timing decisions based off the physical placement of the logic. In fact, we achieved worse results when we entered the constraints directly into a UCF file (bypassing the synthesis tool).

Area Groups
You can enter the area group constraint through SCOPE by selecting the attributes tab. Each cell in SCOPE has a pull-down menu with only the correct values available. As shown in Figure 3, the “s_” instance is found and the xc_area_group constraint is selected.

After several iterations, we found a good area group constraint that worked well with ISE software, producing a minimum period of 187 MHz. We continued this iterative process, trying area groups on different instances as well as trying different PAR cost tables (a PAR cost table gives a different starting point for the place and route process).

Ultimately, we placed area group constraints on two instances inside of “s_” and used a PAR cost table setting of 8 to get the final minimum period of 189 MHz, close to the arbitrary goal of 190 MHz and a significant improvement over the unconstrained design speed of 115 MHz.

As a final confession, we used the NCF period constraint of 220 MHz. Using the actual constraint of 190 MHz decreased design performance after implementation from 189 MHz to 180 MHz. This is not normal behavior from PAR. Over-constraining in PAR can have the same detrimental results as over-constraining in synthesis, so a design with a positive effect of an over-constrained period in PAR represents a corner case.

Conclusion
Our design was small and easily fit in the smallest Spartan-3 device. However, using the same methodologies outlined in this article, a significantly larger design can meet timing using Synplify Pro’s constraints and switches and passing those constraints to ISE software.

Using the switches in Synplify Pro software, SCOPE, and Xilinx Floorplanner, our design met the arbitrary goal and a significant timing closure on a Spartan-3 design.

For more information, visit www.synplicity.com/products/synplifypro/index.html and www.xilinx.com/spartan3.

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