Every designer ultimately needs to finish their design on time and on budget while meeting performance requirements. Xilinx® courses provide you with the necessary knowledge to deliver your projects predictably and within budget.

Xilinx Education Services provide six curriculum paths that focus on a specific area of design specialization: Languages, FPGA Design, PCI Design, DSP Design, High-Speed Design, and Embedded Design. In this article, we’ll explore the FPGA Design path and show how each course builds on itself, from fundamentals to achieving high-performance design objectives.

For example, our FPGA series of courses offers you a successful step-by-step timing closure strategy. In addition to increasing performance, this has the added benefit of reducing power because of less routing. All of our logic courses offer you best practices, tips, and techniques for utilizing Xilinx ISE™ software, cores, and architectural features. The following course descriptions describe some specific design challenges that you will tackle.

Fundamentals of FPGA Design Course
Fundamentals of FPGA Design covers basic hardware and software features, coding tips, design performance, and reliability.

Does your in-circuit functionality change from one implementation to the next? Are you struggling with reliability issues? Through concise asynchronous and equivalent synchronous design examples, this course will show you how to avoid circuit reliability pitfalls and replace them with reliable synchronous circuits. Synchronous design techniques provide reliability, structure, and lay the foundation for increasing performance.

Do you struggle with creating early pin constraints for your FPGA? Using PACE (the Pinout Area and Constraint Editor) for creating pin constraints, you can take advantage of the FPGA fabric rather than creating a bottleneck in performance.

Wouldn’t it be nice to have complex cores already created and optimized for Xilinx FPGAs? You will use the Xilinx Architecture Wizard to optimize cores for instantiation.

You will learn to:

• Use Xilinx ISE Project Navigator to implement an FPGA design
• Read suitable reports to determine whether design goals were met
• Assign pin locations with PACE to enhance performance
• Configure a clocking scheme with the Architecture Wizard software
• Use the Constraints Editor to create global timing constraints, which drive performance
• Specify software options that can boost performance
• Use synchronous design techniques to create reliable designs and improve performance

Designing for Performance Course
Are you having trouble meeting your performance goals? Do you find that changing software options doesn’t help – or makes matters worse? In the Designing for Performance course, we will teach you a simple timing closure flow (see Figure 1), as well as which options to use and what to expect.

For example, say that you need to increase your performance by 25%. What should you do? Using the techniques taught in this course, you can take a design that can barely achieve 125 MHz performance and by the end of the course increase performance to 200 MHz – an increase of 38%.

Are you having trouble synchronizing an incoming signal? Do you need to cross data from one clock domain to another? In this course, we will further explore synchronous design techniques, teaching you how to pipeline, duplicate high-load signals, and use synchronization circuits.

Do you find that your synthesis software settings do not always accomplish what you would like? Are you not certain what each option does? Utilizing synthesis settings, you can increase the lab design’s performance by as much as 20%. Does your design have multi-cycle and false paths? By correctly constraining the lab design with multi-cycle and false path constraints (see Figure 2), you will find that the design runs 20% faster than originally noted. Correctly constrained, your design may benefit by even greater amounts.

How do you find failing timing constraints – and how do you fix them? Understanding how to use the information provided by Xilinx Timing Analyzer is the central catalyst to increase the course’s lab design performance by 38%.

How do you use the myriad of implementation settings to improve results? Do you need to increase your performance by 2%, 10%, or more? You will identify which advanced implementation options provide the most benefit for each situation.

You will learn to:

• Write HDL code to efficiently target Virtex™-II-based device resources
• Create customized and optimized cores in CORE Generator™ software
• Use Timing Analyzer to pinpoint timing errors and identify a strategy to improve performance
• Use design/coding techniques and software options to achieve timing closure
• Correctly and completely constrain your design with global and path-specific timing constraints in the Xilinx Constraints Editor
• Improve design performance and manage software runtime by using the optimal software settings

Prerequisites for this course include Fundamentals of FPGA Design and basic VHDL or Verilog knowledge.

Designing with the Virtex-4 Family Course
At this point, you have taken Fundamentals of FPGA Design and Designing for Performance, but you want to design into the latest and greatest device, the Virtex-4 FPGA. The next course, Designing with the Virtex-4 Family, has an emphasis on teaching you to obtain the highest possible performance (up to 500 MHz internally) and reduce power consumption. This course covers a myriad of new and enhanced capabilities of the Virtex-4 FPGA fabric, with a major emphasis on lab exercises.

How do you utilize the new DSP48 resource for arithmetic operations? How do you utilize it for DSP applications? In lab exercises, you will use the DSP48 for DSP and arithmetic applications requiring 500 MHz operation. Did you know that you can also use this resource to implement logic resources such as a 6:1 multiplexer? We will give you the necessary information to take advantage of this dynamic, highperformance, and low-power resource.

How would you design a clocking scheme with ten global clocks and six regional clocks? In lab exercises, you will use the new Xesium clocking resources (see Figure 5) to design a complex clocking scheme in Virtex-4 devices. This includes utilizing the enhanced DCM, new phase-matched clock divider (PMCD), enhanced global clock buffers (BUFGCTRL), and new regional clocking resources (BUFIO and BUFR).

Have you heard about the block RAM performance enhancements and dedicated FIFO resources? You will create a 500 MHz block RAM core employing the new optional output register. You will also create a core utilizing the new dedicated FIFO16 resources.

Do you need to design a source-synchronous interface? The new Virtex-4 IOB tile includes ISERDES and OSERDES resources. You will examine the use of the new Xesium clocking resources and the ISERDES/OSERDES resources for creating your own source-synchronous interface. You will also learn about the available automated tools, ChipSync wizard, and memory interface generator (MIG) for creating source-synchronous interfaces.

You will learn to:

• Utilize the Xesium global (32) and regional (2 per region) clock networks
• Dynamically reconfigure the DCM’s frequency synthesized output (CLKFX) and fine phase shift (DPS)
• Create phase-matched divided clocks using the new PMCD
• Create customized source-synchronous interface cores with the ChipSync wizard or memory interface generator (MIG)
• Increase the performance of your memory resources using the new Virtex-4 block RAM and FIFO16
• Increase performance and reduce power of your arithmetic and DSP circuits utilizing the DSP48 resource

Advanced FPGA Implementation Course
Building on the knowledge of the three previous courses, Advanced FPGA Implementation tackles the most sophisticated aspects of the ISE tool suite and Xilinx hardware. This course covers varying topics to help you achieve better results, make changes faster, and maintain your results. Lab exercises are 50% of class time, increasing your knowledge and skills through experimentation.

After each small design change, do you get frustrated when you have to completely re-implement a design? Do synthesis and implementation take too long? Do your timing results change? In lab exercises, you will use incremental design techniques (see Figure 3) for an incremental design change, preserving your previous timing results. This can reduce your iterative synthesis and implementation run time by as much as 50%.

Are you ready to create an implementation layout? You will use Floorplanner or PACE to create a design layout to increase the performance of your design. Additionally, these tools are used for designs employing incremental design techniques.

Do you have a design that uses more than eight clocks? In Virtex-II-based devices, many clocking features are available, but you must also consider their effects. In lab exercises, you will use a simple step-by-step strategy to design a complex multiple-clock clocking scheme in a Virtex-II device, taking advantage of all of the features available. The Virtex-4 clocking resources are also introduced.

Are you having trouble meeting timing on a particular path in your design? You will identify when and how to create a relationally placed macro (RPM) for problematic timing paths in your design. An RPM ensures predictable performance results for each included element. In the lab exercise, you will use an RPM to meet performance objectives for a critical path.

Do you prefer to use scripts rather than GUIs? With the techniques, strategies, and options covered, you will learn the most effective switches for improving performance. You will also use the settings and options in the scripting lab to greatly improve the performance of the design.

You will learn to:

• Create and edit timing and placement constraints to increase performance
• Build RPMs to improve performance on critical paths and achieve predictable timing results on complex functions
• Implement efficient clocking schemes for Virtex-II and Spartan™-3 FPGAs
• Use incremental design techniques to shorten the design cycle and maintain performance results
• Quickly modify implemented designs in FPGA Editor for more efficient incircuit testing
• Use scripts and software options to increase performance and reduce area
• Use a systematic timing closure strategy to achieve optimum performance

Your design goals equate to our teaching objectives. Only the most qualified and experienced instructors and design engineers qualify to teach this class. Instructors tailor the instruction and discussion within the framework of the class to help you achieve your personal learning objectives. This course requires Fundamentals of FPGA Design and Designing for Performance as prerequisites. An intermediate knowledge of Verilog or VHDL is strongly recommended, as is at least six months of design experience with Xilinx FPGAs.

Conclusion
Our goal is to help you achieve your design goals in the shortest possible time. To do that, we believe we have created the most comprehensive set of courses in the industry to accommodate your complex designs and goals. You can spend days and even weeks trying to accomplish your goals without really learning to quickly, correctly, and strategically use the software and hardware. Rather than waste your time and money, come and learn how the pros do it.

For a comprehensive list of training courses available worldwide or to take a skills assessment to find out what courses you need, go to http://xilinx.com/education, or click on the “Education” link from the support website (the curriculum path for FPGA Design is shown in Figure 4). We truly believe in what we do and what we can help you to do with Xilinx devices.

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