The increase in FPGA densities is giving rise to more than just substantially larger logic arrays. Today’s FPGA designs incorporate an increasing amount of tightly integrated hard IP blocks – a trend that creates new challenges for design software. One of the most critical challenges is the difficulty of traditional logic synthesis tools to correctly predict the critical path of the design as geometries shrink and wire delays become predominant.

The latest advances in logic synthesis now make it possible to use the integrated DSP blocks of Xilinx® Virtex™-4 FPGAs at their full potential. Physical synthesis has emerged as the key new technology to reconcile the RTL optimization effort with performance bottlenecks seen at the placement stage.

In this article, I’ll consider these and other new software challenges posed by state-of-the-art FPGAs, and how Xilinx and its software partners Synplicity and Mentor Graphics are responding.

A Two-Fold Challenge
Most large designs are compiled from the top down. Given their size and complexity, it is not uncommon for such designs to engender several potentially critical paths. As a result, when operating predominantly from inaccurate estimations based on empirical wire-load models, a synthesis tool might optimize paths that are in fact not critical and not consider others that truly could be critical.

A second challenge for synthesis tools is inferring larger hard IP elements (memory or DSP blocks) found in Virtex-4 FPGAs. When you need to keep the RTL code for a given project portable (as is often the case), the burden is on the synthesis tool to generate excellent results based on that portable code. It must be able to accurately map the logic onto the hard IP blocks.

New Software Tools and Optimizations
Physical synthesis offers a solution to reconcile front-end optimizations with the actual results derived from performing place and route. Physical synthesis tightly couples synthesis and place and route by making synthesis aware of actual timing bottlenecks early in the design. It ensures that synthesis optimizations are effectively applied to the appropriate places and interacts with placement to deliver superior results. This technology does not require manual intervention and can be used in “push-button” flows.

Physical synthesis algorithms are now available in Xilinx ISE™ 8.1i software. Precision Physical from Mentor Graphics and Synplify Premier from Synplicity also provide physical synthesis capabilities. The latter uses an innovative approach called “graph-based synthesis” in which placement takes into account the available routing resources. Synplify Premier offers this technology to Xilinx FPGAs only.

Synthesis also addresses the use of more sophisticated hard IP blocks by providing inference algorithms that understand the detailed structure of the FPGA. This recent enhancement enables the tools to effortlessly produce pure RTL descriptions, yielding 500 MHz predictable performance without the need for instantiation.

To provide the best push-button results, Xilinx also provides a multi-compile script called Xplorer. Xplorer has two modes: the first one attempts to obtain the maximum performance for the design, while the second one works within the designer’s constraints to meet timing. In this second timing closure mode, Xplorer applies different algorithms for logic packing and place and route, and reports the best settings for future design iterations.

Think Hardware
Successfully coding RTL for performance requires silicon considerations. Once you “think hardware,” your RTL description directs synthesis to use specific silicon functions. Consider the integrated XtremeDSP™ blocks in Virtex-4 FPGAs. They enable ASIC performance, but that performance can be severely impacted if the RTL coding style implies an asynchronous reset. That’s because the native reset of the block is synchronous. Using a synchronous reset enables registers to be merged into the block, thus improving performance (and area) to a large extend.

Regardless of software tools, coding styles are essential. Combined with synthesis tool constraints, options and synthesis directives can drastically affect performance.

PlanAhead
FPGAs offer specialized resources that designers must manage to create an optimal solution. For example, you may want to align certain blocks to a given clock domain using specific resources, or group the design critical path logic to ensure a tight implementation of those resources. This requires more than a simple improvement to the “push-button” synthesis solution.

Xilinx offers a tool called PlanAhead™ software that provides just this type of resource management. PlanAhead software has an intuitive graphical interface that lets you browse the logic hierarchy of a design to create an optimal connection to the physical layout of the targeted device.

Additionally, PlanAhead design tools can help generate IP blocks and make it simple for you to export them to other designs. PlanAhead software also makes it easy to use advanced block-based flows such as incremental design, modular design, or even flows involving reconfigurability.

Conclusion
The evolution of larger, more complex FPGA designs with increasing amounts of hard IP poses a substantial challenge to tool suppliers. Advances in areas such as physical synthesis and new inference algorithms make the full performance potential of next-generation FPGAs accessible at virtually the push of a button, while PlanAhead software places the full suite of FPGA resources at your fingertips – even for the most complex, block-based design flows. The Xplorer script provides the most efficient path to discover the maximum performance or timing closure.

Other articles in this edition of the Xcell Journal will provide more details on these topics, including coding styles, the physical synthesis capabilities of ISE 8.1i software, Synplify Premier, the Xplorer tool, and PlanAhead design tools.

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