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As FPGAs become a viable option for high-performance
signal processing in the digital
communications design space (cellular base
stations, satellite communications, and
radar), analysis and debug tools must
include new techniques to help you get the
most optimal performance in your circuits
in the least amount of time.
Although signal analysis tools that connect
to simulation and RF analog signals
are available, it’s important to be able to
measure signal quality (frequency spectrum,
I-Q constellation, and error vector
magnitude [EVM]) in the sub-circuits of
your FPGA. Thus, Agilent has linked its
89601A Vector Signal Analysis (VSA) software
with its line of logic analyzer products
(1680, 1690, and 16900 families) to create
a digital VSA tool. This tool, when combined
with the Xilinx® ChipScope™ Pro
Agilent Trace Core, allows you to perform
signal analysis anywhere inside your FPGA
design quickly and easily.
In this article, we’ll show how this combination
of tools works – and how it can
help you get the most from your Xilinxbased
DSP circuits.
Digital VSA
VSA uses Fast Fourier Transform (FFT)-
based data processing to provide a combination
of time- and frequency-domain
displays and measurements. Figure 1
shows a typical VSA display. Although
the display is extremely flexible and configurable,
the main components include
the I-Q constellation plot (upper left),
magnitude spectrum (lower left), error
vector (upper right), and measurements
(lower right). The EVM is displayed in
the measurements section. This single
value is a key indicator of the quality of
the modulated signal.
EVM is computed by extracting I-Q
symbols from the captured data; the symbols
are the grid points in the constellation
defined by the QPSK, QAM, or
other modulation scheme. Once extracted
from the measured signal, the symbol
sequence is used to create an ideal (theoretically
perfect) signal known as the “reference”
signal. Each measured signal is
compared to the reference signal, and the
difference is known as an error vector.
(The error can contain both I and Q, or
magnitude and phase components). The
individual error vectors for a single capture
are combined to make a single EVM
measurement.
Although this analysis software was
originally created to analyze analog RF
signals, it was developed in a hardware-independent,
PC-based software package.
Because Agilent logic analyzers are also
PC-based, it was easy to extend the VSA
software to link to the logic analyzers.
Digital baseband and IF signals are representations
of analog signals. Rather than
using an instrument that digitizes a signal
to enable FFT analysis (like an RF signal
analyzer), the signal is digital from the
start. These digital versions of analog signals
can be displayed in a logic analyzer in
a chart-style waveform, which resembles
an oscilloscope display (as in Figure 2).
As you can see, when the bus is synchronously
sampled and the sample rate
meets the Nyquist requirements, the logic
analyzer captures a sufficiently accurate
version of the “once-was” or “will-soon-be”
analog signal.
FPGA Dynamic Probe
The FPGA Dynamic Probe, working with
the ChipScope Pro analyzer, can provide
access to any part of a DSP design without
recompiling. In Figure 3, a simplified digital
radio transmitter design is connected
to the Agilent Trace Core 2 (ATC2). This
core is a switching MUX incorporated
into the design using the ChipScope Pro
Core Inserter, typically post-synthesis.
During core insertion, you select the
internal nets to connect to the trace core,
and the physical pads to which you will
connect the MUX output. These pads are
then routed on the circuit board to
a logic analyzer probe.
The logic analyzer controls the
FPGA through JTAG (downloading
the bit file and selecting banks).
When you select a new bank, the
logic analyzer automatically reconfigures
itself to match the names of the
nets now connected to the probe.
Design Example – QAM16 Modulator
With help from our local Xilinx
DSP specialist FAE, we created a
demo that fits into a small Virtex™-II part (XC2V250-FG256) using
Xilinx System Generator for DSP.
This tool makes creating DSP
designs quick and easy. The design
(shown in the block diagram in
Figure 3) contains a 25 MHz symbol
encoder; a root-raised cosine filter
with 24 taps and 4X interpolation
(the output running at 100 MHz);
and an IF modulation stage with a
25 MHz local oscillator.
Integrating the ATC2 Core
in a System Generator Design
After compiling this design into
VHDL, we inserted the ATC2 core.
To make the signal names more logical
on the logic analyzer display, we
did some hand-editing of the VHDL.
(You could avoid this step by carefully
choosing net names in the System
Generator.) We then connected most
of the interesting nets as output ports
from the top-level object to make the
net names short enough to fit on the
logic analyzer screen.
When connecting nets to output
ports solely for use with the FPGA
Dynamic Probe, a good trick is to use
the “keep” attribute in the VHDL.
Because you don’t add the ATC2 core
to the design until after synthesis,
many nets would otherwise be optimized
out because they’re not connected
to anything. In VHDL, the
syntax to use the “keep” attribute
looks like this:
attribute keep : string;
attribute keep of i_symbol: signal is “true”;
attribute keep of q_symbol: Signal is “true”;
We created an ATC2 core with
four banks, each with 48 signals.
Using the ATC2 core’s 2X TDM
option (time-slicing two signals at a
time on each pad), this requires only
25 package pads on the FPGA (one
for a clock and 24 for data). This gives
us access to 192 signals. Actually, we
only need to view about 92 signals:
- I-Q symbols, 8 bits each (16)
- I-Q filter output, 24 bits each (48)
- IF local oscillator sine and cosine, 2 bits each (4)
- Combined IF signal (24)
The output of the RRC filter with
24-bit I and Q signals was the largest
requirement, defining the number of
pins required. If 24 pins were not
available, you could drop the least significant
bits, losing some dynamic range
but still being able to view the signals.
Time-Domain, Logic,
and VSA Measurements
The logic analyzer uses synchronous
sampling (or “state mode”) to capture
the output of the ATC2 core. This
means that data is sampled on each
edge of the ATC2’s output clock. Our
design has two clock rates in the circuit
– 25 MHz for the symbol data before
the RRC filter and 100 MHz for all
parts after the filter. Because the ATC2
core supports only one clock per core,
two options exist for debug:
- Using two cores, one for each
clock rate
Using one core with the faster
clock rate and over-sampling the
25 MHz bus
Because the two clocks are correlated
– and one is an integer multiple of the
other – you can just over-sample the
slower bus. If over-sampling is not desirable,
the logic analyzer can use a setup
that stores every fourth sample, thereby
capturing the 25 MHz bus accurately
with one sample per 25 MHz clock.
With the extra signals available in
the MUX, we were able to doubleprobe
some of the interesting signals.
For example, in bank 0 we have the I
and Q symbols before the filter, and
also the I component after the RRC filter.
This means we can do some timedomain
analysis in the logic analyzer to
measure group delay in the filter, as in
Figure 4. Two markers indicate a common
signal feature: a wide, flat top and
the marker measurement display showing
an interval of 250 ns.
After probing the interesting parts of
the circuit, we performed vector signal
analysis on the signals and measured the
quality of our RRC filter and IF modulation
stages.
Looking at the QAM16 I-Q symbols
before they were filtered (as shown in
Figure 5), you can see the 16-point
QAM constellation (upper left graph).
With one point per symbol, the lines
between the constellation points are
straight. The frequency spectrum (in the
lower left graph) is centered at 0 Hz and
has a 25 MHz pass-band with power in
adjacent channels. Adjacent channel power
is undesirable in the RF signal, of course,
which is the reason for the baseband filter.
By selecting a different bank in the
ATC2 core (controlled by the logic analyzer),
you can perform analysis on the IQ signal
after the baseband filter, as seen in
Figure 6. Now the spectrum has sidebands
removed, and the measurement display (in
the lower right quadrant) shows an EVM
of 0.5%. The next time your RF team complains
of errors in the baseband design, you
can point to this measurement (with which
they are quite familiar), and prove that it’s
not your filter’s fault.
In many digital radio designs, this IQ
signal would now be converted to analog.
However, we performed the IF modulation
digitally inside the same FPGA. Switching
banks in the FPGA Dynamic Probe gives us
access to the digital IF (again, without
another synthesis and place and route step),
as shown in Figure 7. Note that the spectrum
and I-Q constellation are roughly the
same, only now centered about 25 MHz.
The EVM is a little bit higher, indicating
that you may want to use a higher quality
local oscillator or another filter stage.
Conclusion
Xilinx System Generator and ChipScope
Pro analyzer, combined with the Agilent
logic analyzer and Agilent VSA software,
allow you to perform real-time in-depth
analysis on digital baseband and IF signals
inside your Xilinx FPGA. This will save
you time and eliminate doubts about the
difference between simulation and real
hardware. It can also help you communicate
with your colleagues on the RF design
team, enabling you to speak their language
and use the same analysis software regardless
of signal format (analog, digital, baseband,
or RF).
For more information about these
applications, visit www.agilent.com/find/logic-sw-apps, or contact your Agilent
representative.
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