The Optical Networking Products Division at Lucent Technologies is involved in producing next-generation SONET optical networking equipment for Internet service providers. Our current project adheres to the OC48 standard, with serial I/O as high as 2.5 GHz. Internal logic clock speeds can run anywhere from 155 MHz on down, with heavy system interface and bus traffic on our system boards.

Our past projects have relied heavily on HDL simulation, using VHDL models for component modeling and bus functional models to simulate the interface and backplane traffic. To accurately model the entire system, we also added external memory interface device models and modeled the effects of interface trace delays. Together, this system simulation would let us check new design concepts in our existing and future projects. The downside was that we had to create HDL test benches and maintain them in parallel. System simulation times could be quite long and tedious, and there remained the unanswered question, “Have we modeled enough to accurately predict system behavior”?

ChipScope Pro Analyzer – Real-Time Debugging
We began using Xilinx® ChipScope™ Pro in our systems with the 6.1i software release. In our current project, we are using two to three ChipScope Pro ILA cores per clock domain inserted into our target Virtex™-II Pro XC2VP30 device. The soft debug cores are inserted after the synthesis stage using the ChipScope Pro netlist inserter, and we debug primarily by using the ChipScope Pro logic analyzer. We are capturing roughly 100 transitions in any one debugging cycle, depending on the particular problem we are researching, and we use trigger ports to save onboard block RAM memory.

ChipScope Pro tools let us capture data at any point in the FPGA, while the chip is interacting with the rest of the system and running at operating speed. We have been able to reduce the number of pins on the FPGA and on the board that were previously dedicated to verification, since we debug directly through the JTAG programming cable.

Uncovering Problems
One example, in which by using the ChipScope Pro analyzer we debugged a problem that we wouldn’t have otherwise uncovered, was in a new revision of one of our in-production products. At the vendor’s recommendation, our manufacturer had recently upgraded one of the system’s external memories. Suddenly we were seeing degraded performance and memory parity errors. Nothing else had changed, yet the system stopped working. Simulation didn’t reveal the error, but we started tracing through with the ChipScope Pro tools, in real time. By triggering on the parity byte, we were able to discover a handshake problem when writing data to and from the controller. We were issuing an autorefresh before bank pre-charge before a write cycle was complete. This was fine in the older part, but the tolerances had changed slightly in the new part.

Conclusion
We still use HDL simulation in our projects here at Lucent, but ChipScope Pro tools have now become a vital part of our design and verification cycle, for all of our projects. By catching problems in real time in the lab and by taking advantage of the reprogrammability of FPGAs, we are able to turnaround design problems in a matter of hours and get more out of our project time.

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