Design problems – especially those characteristic of large, high-performance designs – are most effectively addressed by first investigating the problem and then breaking the larger design issues into smaller, more manageable hurdles. Looking at the evolution of programmable devices in recent years, it is apparent that FPGAs have undergone tremendous growth in size and complexity, but the PLD EDA tool flow has remained relatively unchanged.

With a traditional flat design flow, each design change means re-synthesizing and reimplementing the entire design. With complex designs on multi-million-gate devices, even a minor change can lead to unacceptably long place and route (PAR) runtimes, which itself often leads to inconsistent results, not to mention the time lost from RTL to PAR iterations for a typical design.

Few design teams can tolerate unexpectedly low performance for a design that took longer than expected to complete, not to mention the associated frustration and stress. In addition, it may mean low utilization of the FPGA and even missed time-tomarket opportunities.

PlanAhead Software Offers a Solution
A growing number of customers are finding a solution in the hierarchical design methodology offered by the Xilinx® PlanAhead™ design analysis tool. PlanAhead software adds visibility and control to the FPGA design flow. By addressing problems on the physical side (between logic synthesis and the implementation process), you can realize improved performance in your results.

Although advanced FPGA synthesis products provide a tremendous level of automated optimization for multi-milliongate designs, many designers require more heuristic techniques to achieve optimal performance goals. Through early analysis and floorplanning, PlanAhead design tools can apply physical constraints to help control the initial implementation of the design. After implementation, PlanAhead software can analyze placement and timing results to improve the floorplan used to complete the design. You can use the physical constraints derived from the imported results to lock placement during subsequent implementation attempts. These constraints can be used to create reusable IP, complete with locked placement, for other designs.

The PlanAhead design methodology provides performance, productivity, and repeatability of results. With its hierarchical design flow, PlanAhead software allows you to reduce the number of iterations spent running PAR and then returning to RTL and synthesis. Instead, you can analyze your design and address issues on the physical side before implementation.

Faster Results in Less Time
PlanAhead users are consistently seeing a 10-15% performance improvement, with some achieving much higher results. In addition, designers are also finding that they can squeeze an additional 10% logic into a tight device. This combination of faster performance and better utilization can translate into a smaller, less expensive device, or design goals achieved with a slower speed grade.

PlanAhead design tools help reduce overall design time while adding a level of consistency in the results. You can perform design iterations in much less time – with repeatable results – by leveraging previous floorplans or incremental design techniques. You can also leverage successful results by locking them down or reusing them in other designs.

Tackling really tough performance issues requires more than just the addition of new menu items or scripting capabilities. PlanAhead software provides a complete environment to make this hierarchical methodology interactive and easy to use by presenting design data through the use of various views (see Figure 1). These independent views are designed to work in conjunction with each other, allowing you to quickly identify and navigate critical design objects and information.

Visually Identify Performance Bottlenecks ...
The PlanAhead environment provides insight into the data flow of the design by displaying I/O interconnect as well as physical block (or “Pblock”) net bundles. You can control color and line thickness of the bundles depending on the number of signals. This makes it easy to identify heavily connected Pblocks in the overall data flow through the design. You can then take corrective action to avoid routing congestion trouble spots and place heavily connected Pblocks close together, or merge them.

Clock regions are also displayed and can be used during floorplanning to optimize various clocks or minimize power usage within the device. By isolating clocks to specific clock regions, they can run faster and eliminate the need to power up other clock regions.

You can use the analysis and exploration environment of PlanAhead design tools at various stages in the design process. Initially, you can analyze the design before implementation. PlanAhead software provides a static timing engine, TimeAhead, that examines the design’s feasibility relative to timing. You can also perform analysis using estimated routing delays by factoring in pure logic delays with no interconnect. This allows you to see how much timing tolerance is built into the design.

You can then edit and fine-tune timing constraints within the PlanAhead environment. These same analysis results can help determine what logic should be grouped together and floorplanned. Paths can be logically sorted, grouped, and selected for floorplanning. The same TimeAhead environment can also be leveraged with imported timing results from TRCE, the timing evaluation tool within Xilinx ISE™ software.

The timing constraints assigned to the design can be viewed and modified. You can define all ISE timing constraints as new constraints within the editor. This makes constraint assignment easier because you no longer have to remember specific constraint formats. You can use this with TimeAhead to validate and optimize the constraint set before running any ISE implementation tools.

PlanAhead design tools provide visual aides to help you comprehend the physical implementation results. Design rule checks (DRCs) are provided to catch errors early. It also flags designs that do not properly take advantage of certain device resources, such as the dedicated registers of the XtremeDSP™ slice or RAM within the Virtex™-4 FPGA.

By visualizing problem areas, you can address problems quickly, either in the RTL or on the physical implementation side, without having to continue RTL and synthesis iterations. The various logic modules can be selectively highlighted to better understand where they were placed, and Pblocks created where the logic is most concentrated. You can highlight failing timing paths to visualize and understand what is physically happening within your design.

PlanAhead software has includes metric maps to quickly identify problem areas of the design (Figure 2). These can be related to timing or utilization. This is helpful when trying to identify areas of the design to focus on for logic compression or timing connectivity.

PlanAhead design tools allow you to explore connectivity within the design. After selecting a particular net, Pblock, or instance within the design, you can highlight all of the nets connected to the selected elements with a single mouse click. After an instance or Pblock is selected, all of the nets connecting to that element will be highlighted. This process can be continued, selecting and expanding the logic cone. Running “Show Connectivity” will highlight the next level of nets connected to the selected instances. This is an easy way to select a cone of logic starting at a particular instance or I/O port, taking real advantage of the design hierarchy.

... Then Address the Performance Problem
The whole idea is to provide a comprehensive environment to analyze timing issues and easily constrain that logic to avoid or correct it. You can use timing results from either TimeAhead or TRCE to drive a floorplan that will produce better performing designs by helping determine what logic should be grouped together and floorplanned.

Critical paths often traverse the logic hierarchy. PlanAhead software enables a physical hierarchy that is independent of the logic hierarchy, allowing logic from anywhere in the design to be grouped together and efficiently floorplanned.

PlanAhead software also provides resource utilization estimates to help size and shape Pblocks. These same statistics report clock information, carry chain, and RPM sizes for fit and a variety of other useful information.

PlanAhead design tools provide automatic floorplanning capabilities such as automatic partitioning based on the logic hierarchy and automatic Pblock sizing and placement. Because it is often difficult to encompass the required device resources within a single Pblock rectangle, nonrectalinear shapes can be created with multiple rectangles. PlanAhead software also allows you to create Pblocks within Pblocks, or “child” Pblocks, to help better maintain design hierarchy.

Device capacity can be improved by compressing the logic with Pblocks. This can be achieved in one of two ways. One is to use the Xilinx AREA_GROUP attribute called COMPRESSION. AREA_GROUP is a design implementation constraint that enables partitioning of the design into physical regions for mapping, packing, placement, and routing. Using the COMPRESSION attribute will cause the ISE Mapper to pack unrelated logic into unused CLB sites. Use this with care, as it can have an adverse affect on timing.

The best strategy for improving performance is to compress non-timing critical logic, thereby opening up more space in the device for timing critical logic. The second option is to use the PlanAhead capability to run PAR on Pblocks individually. You can continue to shrink the Pblock size until PAR fails. This will reduce and pack the logic as tightly as possible within the blocks and free up device space.

A Virtex-4 Floorplanning Example
PlanAhead design tools allow you to easily import placement and timing results. With this information, you can view and sort critical paths from the timing report and visualize paths using either the schematic or device views. Once you’ve identified failing paths, you can highlight all path instances on the floorplan to identify all path instances in the schematic view.

Figure 3 shows a floorplan of a design targeting a Virtex-4 FX140 device. In the display, we’ve highlighted the flip-flops along a particular path that was not able to meet timing. Because they are so widely distributed across the device, design implementation results in an unacceptably long delay. With the large number of clock domains available in Virtex-4 FPGAs, this is a common situation.

By selecting each of these flip-flops and restricting them to a single Pblock, you can then adjust and optimize the Pblock size and location to reduce delays on critical paths, as shown in Figure 4. If necessary, you can even create nested Pblocks, creating a child/parent hierarchy to further constrain sub-modules for additional performance gains. Depending on the resource requirements of the captured logic, you can lock down critical logic to locations for optimal access to necessary resources.

Conclusion
Visit www.xilinx.com/planahead to download a free evaluation of PlanAhead software today. This 30-day evaluation provides you with full access to all of the PlanAhead features and functionality. This site also allows you to view product demonstrations, download white papers, or just learn more.

Xilinx also offers PlanAhead QuickStart!, an exceptional level of support during the most critical phase of a project. With this service, you will receive a QuickStart! engineer at your site for one week who will train and empower your team to complete your project on time and make best use of the Xilinx device you have selected. This highly customizable service allows you to develop a training plan tailored specifically to the needs of your design team. This will help prevent schedule slips later in the project by ensuring that the team is skilled in the needed disciplines. It will also help you maintain a more effective and highly motivated team.

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