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Timing closure is perhaps the single most
important design issue facing designers
today. With FPGAs and other deep
submicron ICs, routing delays usually
dominate logic delays.
Although there are hundreds of ways
to improve timing, such as using the
embedded PowerPC™ processor or
another high-speed core, the focus here is
on improving performance on the logic and
routing portion of the design. In this article,
I will explore the methodology to achieve
timing closure for Xilinx® designs.
Timing Closure Design Flow
Figure 1 shows a typical flow that starts
with well-written HDL optimized for
FPGA architectures. Xilinx ISE™ software
provides Verilog and VHDL templates to
begin crafting good HDL code. FPGAs
have an abundance of registers, so adding
pipeline stages can greatly improve timing
and have very little impact on area. Some
of the frequently used best practices
include keeping critical paths in the same
entity or module, utilizing clock enables
instead of gated clocks, and avoiding the
use of latches, nested for-loops, and if-then-else statements in the HDL code.
Xilinx also recommends using synchronous
resets for modules such as DSP48,
FIFO16, and block RAMs, and using
adder chains instead of adder trees to help
achieve 500 MHz DSP48 performance
(illustrated in Figure 1). A comprehensive
discussion on coding styles can be found in
the article, “HDL Coding Practices to
Accelerate Design Performance.”
Synthesis
The flow continues with synthesis, which
provides an early indication of whether or
not your HDL has a chance of meeting timing
and area requirements. Make sure you
constrain timing in the synthesis tools to
avoid minimizing area at the expense of timing
– something that will likely occur if the
tools are given no other direction. At a minimum,
constrain your clocks and I/O paths.
You can also allow the synthesis tools
to try harder by indicating an optimization
effort. Another frequently used
option to meet timing requirements is
register balancing, which moves registers
forwards or backwards through logic to
increase clock frequency. If the synthesis
tools indicate that timing cannot be met,
or if timing is very tight, you may be able
to further optimize your HDL code by
using one or more of the coding techniques
previously discussed.
Implementation
Having obtained an acceptable
timing estimate from the synthesis
tool, use the implementation
tools (map, place, route,
timing analysis) to determine
the true timing of the design.
Xilinx ISE tools, powered by
Fmax Technology, proactively
attempt to achieve the best performance
possible, but do
require that constraints are complete.
A recommended set of
timing constraints (as shown in
Figure 2) should include clock
period, I/O offset, multi-cycle
path specification, and timing
ignore (TIG) to ignore false
paths. If you are missing timing
by more than 20%, you may need to do further optimization of your
HDL, especially within the module containing
the worst-case path.
If you still haven’t met your timing
requirements in the implementation
phase, there are many tool options that
can provide dramatic improvements. A
good starting place is the use of retiming
in your synthesis tool. Another option is
to turn on retiming and global optimization
in ISE Mapper.
Xplorer Utility
Xilinx recently introduced a new utility
called Xplorer that delivers optimal
design results by employing smart constraining
techniques and a variety of
physical optimization strategies. You can use the Xplorer utility to automatically
try these (implementation tool) options
and even try different clock frequencies to
find the maximum achievable speed of
the design. Once Xplorer has found the
best tool options, you should use those
options the next time you run the implementation
tools, avoiding the long runtimes
of Xplorer. You can learn more on
how to achieve the best performance with
Xplorer in the article, “Accelerate Design
Performance Using Xplorer.”
PlanAhead Design Tools
If you’ve tried everything and still can’t
reach that timing closure pinnacle, there is
still hope. The Xilinx PlanAhead™ tool
can be used to analyze, and if necessary,
floorplan the design to achieve higher performance
(15% average, but can be as high
as 2X). PlanAhead design tools provide
better insight into the place and route
process. You can quickly examine “what if ”
scenarios, enabling you to identify and fix
potential problems early. You can also
group critical paths and modules to
increase routability through connectivity
analysis and utilization control.
See the article, “Improve Design
Performance Using PlanAhead Design
Tools” to learn more about the capabilities
of this incredible tool. There are many
other advanced techniques like detailed
floorplanning and creating RPMs (relationally
placed macros), but we recommend
you try the ideas in this article first.
Conclusion
Xilinx provides a comprehensive suite of
software tools, powered by ISE Fmax
Technology, that you can use to improve
design performance. ISE software, together
with the tips and strategies in this article,
can help you quickly achieve timing closure.
Additionally, we work with leading
third-party synthesis vendors to optimize
designs and improve design performance
for Xilinx devices in their leading synthesis
software. An entire section of the Xcell
Journal has been devoted to achieving
design performance using Xilinx software
tools. Please read the related articles in this
issue to learn more.
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