Once a specification has been defined and authorized, several critical stages remain in every design cycle. The first stage is design entry. HDL coding is the most prominent form of entry when designing platform FPGAs. The code must be written properly for the design to pass through synthesis. Xilinx recommends that designers simulate their HDL before moving on.

The next stage is implementation, with the most important aspect being place and route. Implementation maps the HDLentered design into FPGA building blocks, creating a bitstream. Analysis is required before downloading the bitstream into an FPGA. Downloading the FPGA without this analysis can damage the device, or even the system.

Designs must also meet system timing parameters. If timing is not met after an implementation, then the code, timing constraints, implementation options, or internal logic placement must be changed. Yet adjusting any one of these areas can yield your desired results or further remove you from them.

Determining which area to adjust first can be challenging to design teams, especially those feeling the heat of a deadline. The best design teams are those that can make the necessary changes or corrections the fastest. Once the changes have been made, a final verification or timing simulation is required. If the design does not pass, more modifications are needed.

To the Rescue
Xilinx has the expertise to solve your problem and meet your deadline regardless of your application or specification requirements. Under our Titanium Dedicated Engineering program, Xilinx engineers can successfully:

• Aid designers with embedded processing, timing closure, signal integrity, and DSP challenges
• Assist teams starting their first FPGA design with design flow and fundamentals
• Help with adding a feature to a design that is already at capacity
• Meet a deadline with timing closure assistance

Design Challenges
To create a complete and powerful platform FPGA design requires knowledge, skill, time, resources, and patience. To fully utilize and take advantage of all of the new features of a Xilinx device requires ramp-up time for any design team, regardless of their experience level. A good example of this is Xilinx embedded processing technology. Designing with embedded features requires extra skills and knowledge above and beyond those needed for a successful FPGA design. With time, most capable teams will learn how take advantage of these features, but the competition may learn faster with assistance.

Each design team operates and functions differently, but they all seem to have similar practices and styles. The greater familiarity they have with FPGAs, the easier it is to utilize advanced features like the embedded processor or multi-gigabit transceiver, or to reach desired performance levels. Problems can occur if the team is relatively new or inexperienced. The quicker designers adopt our fundamental design style, the quicker they will complete successful designs. For example, timing verification must be performed before transferring the design in software to silicon. The step is not mandatory, but precautionary.

Success Story
Many ASIC design teams prototype their ideas in an FPGA. This allows them to make changes or modifications without the time and expense of re-spinning an ASIC. One Xilinx customer wanted to implement an ARM processor core and additional custom logic inside a Xilinx device. The design was so large that it had to be split up between two Virtex™-II devices. It can be challenging enough to successfully implement a function in one platform FPGA, let alone splitting it across two of them.

The customer’s design was not meeting timing, nor could they configure their system utilizing our System ACE™ technology. Because two devices were required, board connectivity techniques were critical; the board timing and FPGA timing had to be in harmony for the two devices to function in unison.

There were other several crucial design challenges for this team:

• They were one month behind schedule.
• They had a customer demonstration in six weeks
• System frequency was 15 Mhz below the application’s minimum requirement
• Configuring via JTAG was successful, but not utilizing System ACE technology

After an architecture-specific redesign, the next issue was to apply proper timing and area constraints based on their timing report. The constraints force Xilinx place and route tools to concentrate on the most critical areas of the design. The application engineer also focused on educating the design team so that they could apply these fundamentals on their own during their next design.

The main culprit of the configuration issue turned out to be a faulty crystal oscillator. The frequency was a little lower than what its datasheet specified. Once it was replaced, the FPGAs could be configured via System ACE technology.

Conclusion
Xilinx has encountered and solved almost every presentable difficulty at every stage of the design cycle. Most of the issues and solutions have been documented in a database. In a critical design situation, this knowledge can be the difference between success and failure.

Xilinx will give you personalized access to one of our application engineers for the duration of your choosing. This Titanium Dedicated Engineer will be an expert in the area of your design needs and can provide an understanding of Xilinx design methodologies and techniques. The engineer will provide a solution to your problem, at any stage of the design cycle, and also educate your design team on the steps needed to prevent those issues from recurring.

A Titanium Dedicated Engineer can work at Xilinx, on-site with your design team, or a mix of both. This flexibility allows our engineers to fully understand the needs and requirements of our clients, as well as leverage Xilinx factory resources to resolve problems and accelerate production. For more information about Titanium Dedicated Engineering, call (800) 888-FPGA (3742) or visit www.xilinx.com/titanium/.

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