Xilinx Serial RapidIO End Point solution comprising of RapidIO Serial PHY LogiCORE™ IP, RapidIO Logical I/O & Transport, and buffer reference design is now available on Virtex®-5 LXT/SXT/FXT, Industries leading and most powerful FPGA platform.  In addition to the most advanced, high performance logic fabric, Virtex-5 FPGA contain many hard-IP system level blocks, including powerful 36-Kbit block RAM/FIFO, second generation 25 x 18 DSP slices, SelectIO™ technology with built-in digitally controlled impedance, ChipSync™ source-synchronous interface blocks, system monitor functionality, enhanced clock management tiles with integrated DCM and PLL clock generators, and advanced configuration options. Additional platform dependant features include power-optimized high speed serial transceiver blocks for enhanced serial connectivity, PCI Express® compliant integrated Endpoint blocks, tri-mode Ethernet MACs, and high-performance PowerPC® 440 microprocessor embedded blocks.

Xilinx Serial RapidIO IP support on Virtex-5 FXT enables users to build solutions using highest performance embedded processing blocks. The innovative Virtex-5 FXT platform offers the first FPGA to provide up to two industry-standard PowerPC 440 processor blocks. Each processor, with integrated 32KB instruction and 32KB data caches, delivers up to 1,100 DMIPS at 550 MHz. Tightly coupled to the PowerPC 440 blocks is a new integrated 5x2 cross bar processor interconnect architecture that provides simultaneous access to I/O and memory. Highly integrated, this innovative interconnect architecture includes dedicated master and slave processor local bus interfaces, four DMA ports with separate transmit and receive channels, and a dedicated memory bus interface enabling high-performance, low latency point-to-point connectivity.

Designers can rapidly and easily implement advanced scalable embedded processing applications using the PowerPC 440 embedded processor blocks. The advanced PLB architecture maximizes data transfers between the processor, crossbar and soft IP logic with high-throughput 128-bit interfaces to help minimize system bottlenecks. Also, the enhanced high-performance Auxiliary Processor Control Unit (APU) provides added connectivity for dedicated co-processing engines or custom user defined instructions in applications such as video processing, 3D data processing and floating-point math.

To address the growing demand for higher I/O bandwidth, the Virtex-5 FXT platform includes high-performance, low-power RocketIO™ GTX transceivers capable of supporting data rates from 500 Mbps to 6.5Gbps. Consuming less than 200mW typical power per channel at 6.5Gbps, the GTX transceivers come with many advanced features such as 4-tap DFE receiver equalization in addition to linear equalization and transmit pre-emphasis to improve signal integrity at higher line rates. The new transceiver blocks also include a unique multi-code physical coding sub layer to support both 64B/66B and 64B/67B encoding/decoding schemes saving thousands of logic cells for each channel. In addition, cross-platform pin compatibility enables customers who have designs targeting Virtex-5 LXT and SXT devices to migrate their designs to Virtex-5 FXT devices in order to take advantage of the higher-performance embedded processing and serial connectivity.

The Virtex-5 FXT platform includes innovative Signal Processing capabilities with up to 384 DSP slices and 16.5 Mb of internal memory that can be configured to provide over 190 GMACs of DSP processing performance and 92 tera-bits/sec of memory bandwidth respectively at 500 MHz. This balance of hardware resources maximizes the performance for computation-intensive applications typical of DSP and video applications. The DSP48E slice, available in all XtremeDSP™ Virtex-5 devices, enables higher levels of DSP integration and lower power consumption than previous-generation Virtex devices. Over 40 dynamically controlled operating modes are supported including: multiplier, multiplier-accumulator, multipler-adder/subtractor, tree input adder, barrel shifter, wide counters and comparators.

Xilinx Serial RapidIO IP solution is industry’s most optimized and flexible offering and allows logic designers to build the highest level of performance and functionality into their FPGA-based systems. Xilinx RapidIO technology is also available on Virtex-4FX platform and Virtex-II Pro. The Virtex-4 architecture offers wide variety of flexible features to address all complex applications. The Virtex-4 has hard-IP blocks that include the PowerPC processors, tri-mode Ethernet MACs, dedicated DSP slices, high speed clock management circuitry, and source synchronous interface blocks.

Xilinx Serial RapidIO IP is also supported on Virtex-II Pro, which was industry's first platform for programmable systems to include PowerPCs, 3.125 Gbps serial transceivers and high-performance DSP features such as up to 556 embedded 18x18 multipliers.