Xilinx is now shipping the world's first PowerPC processor with a tightly integrated RapidIO interface. The solution includes RapidIO 8-bit LVDS Physical Layer core and is fully compliant to the RapidIO Interconnect Specification v1.2 & Errata 1, and a reference design to hook up the endpoint to the PowerPC's CoreConnect™ PLB. The Xilinx RapidIO to PLB reference design and accompanying RapidIO to PLB application note is available as part of the Xilinx RapidIO 8-bit LVDS Physical Layer core and is accessible through the RapidIO PHY Layer Core Overview page. 

Key Benefits of the solution are:

• Instant Deployment of RapidIO: System architects can now build their intelligent host controllers and peripherals based on the RapidIO interconnect
• Optimum Performance: In a typical system, the processor spends most time waiting for data to come back from the interconnect. The tight integration between the PowerPC and the RapidIO interface allows balanced I/O and processor performance thereby improving throughput
• Flexibility and System Integration: System architects can now build complete systems based on Virtex-II and Virtex-II Pro, the Platform for Programmable systems. For example, they can now integrate several components such as PCI chipsets, Gigabit Ethernet MAC/PHY chips, memory controllers for multiple applications such as high performance DSP, control plane processing and distributed computing