We have detected your current browser version is not the latest one. Xilinx.com uses the latest web technologies to bring you the best online experience possible. Please upgrade to a Xilinx.com supported browser:Chrome, Firefox, Internet Explorer 11, Safari. Thank you!

AR# 10013

5.1i CORE Generator, Asynchronous FIFO - Glitches are seen on WR_COUNT during simulation


General Description: 

When I simulate an Asynchronous FIFO from Core Generator, a glitch appears on the signal on the WR_COUNT output. This glitch appears both in behavioral simulation as well as timing simulation. 


This behavior exists if the EMPTY flag is high and the WR_CLK is toggling with WRITE_EN on. A circuit resets the WR_COUNT when the EMPTY flag is high, and the circuit then resets itself. However, the EMPTY flag remains high (active) as long as there is no RD_CLK to update it. If the RD_CLK is slow in comparison to the WR_CLK, the circuit constantly sets and resets itself, since the empty_flag is active.


A possible way to work around this issue is to use the EMPTY flag to mask the WR_COUNT.  


Take the output of the WR_COUNT and "AND" it with the inverse of EMPTY. This should mask the erratic behavior of the WR_COUNT when empty is active.  


NOTE: This will cause WR_COUNT to be zero until a RD_CLK comes along the clear EMPTY.


This problem was fixed in 3.1i IP Update #2 (D_ip2).

AR# 10013
Date Created 08/29/2007
Last Updated 05/14/2014
Status Archive
Type General Article